In this work, the use of manufacturing metrology across the supply chain to improve crystalline silicon (c-Si) photovoltaic (PV) module reliability and durability is addressed. Additionally, an overview and summary of a recent extensive literature survey of relevant measurement techniques aimed at reducing or eliminating the probability of field failures is presented. An assessment of potential gaps is also given, wherein the PV community could benefit from new research and demonstration efforts. This review is divided into three primary areas representing different parts of the c-Si PV supply chain: (1) feedstock production, crystallization and wafering; (2) cell manufacturing; and (3) module manufacturing.
Thermally induced void growth in Cu filled through-silicon vias (TSV) has been studied for reliability purposes with x-ray microscopy and finite element model (FEM). A laboratory-based x-ray microscopy combined with computational tomography imaging is demonstrated to have advantages over other methods of inspecting TSVs. We show that the 8-keV x-rays used by Nano X-ray Computed Tomography (NanoXCT™) are capable of imaging voids inside filled vias before and after annealing without cross-sectioning the TSV. A series of TSV arrays filled conformally and from the bottom up were inspected by the x-ray microscope before and after annealing. Pre-existing voids in the seamline were observed in conformally filled TSVs before annealing, while bottom up-filled TSVs do not have a seamline or voids. The same TSV samples were repeatedly annealed at 200, 225, 250 and 300°C. X-ray micrographs after annealing reveal TSVs with pre-existing voids are prone to void growth. In addition, x-ray measurements show the total volume of void growth increased with annealing temperature. A steady-state FEM was developed to understand the void growth phenomenon. FEM suggests high concentrations of vacancies occurring at the pre-existing void area cause void growth.
3D IC integration continues to increase in complexity, employing advanced interconnect technologies such as throughsilicon
vias (TSVs), wafer-to-wafer (W2W) bonding, and multi-chip stacking. As always, the challenge with developing
new processes is to get fast, effective feedback to the integration engineer. Ideally this data is provided by nondestructive
in-line metrology, but this is not always possible. For example, some form of physical cross-sectioning is still
the most practical way to detect and characterize TSV copper plating voids. This can be achieved by cleaving, followed
by scanning electron microscope (SEM) inspection. A more effective physical cross-sectioning method has been
developed using an automated dual-beam focused ion beam (FIB)-SEM system, in which multiple locations can be
sectioned and imaged while leaving the wafer intact. This method has been used routinely to assess copper plating voids
over the last 24 months at SEMATECH. FIB-SEM feedback has been used to evaluate new plating chemistries, plating
recipes, and process tool requalification after downtime.
The dualbeam FIB-SEM used for these studies employs a gallium-based liquid metal ion source (LMIS). The overall
throughput of relatively large volumes being milled is limited to 3-4 hours per section due to the maximum available
beam current of 20 nA. Despite the larger volumetric removal rates of other techniques (e.g., mechanical polishing,
broad-ion milling, and laser ablation), the value of localized, site-specific, and artifact-free FIB milling is well
appreciated. The challenge, therefore, has been to reap the desired FIB benefits, but at faster volume removal rates. This
has led to several system and technology developments for improving the throughput of the FIB technique, the most
recent being the introduction of FIBs based on an inductively coupled plasma (ICP) ion source. The ICP source offers
much better performance than the LMIS at very high beam currents, enabling more than 1 μA of ion beam current for
fast material removal. At a lower current, the LMIS outperforms the ICP source, but imaging resolution below 30 nm has
been demonstrated with ICP-based systems. In addition, the ICP source allows a wide range of possible ion species, with
Xe currently the milling species of choice, due to its high mass and favorable ion source performance parameters. Using
a 1 μA Xe beam will have an overall milling rate for silicon some 20X higher than a Ga beam operating at 65 nA.
This paper will compare the benefits already seen using the Ga-based FIB-SEM approach to TSV metrology, with the
improvements in throughput and time-to-data obtained by using the faster material removal capabilities of a FIB based
on an ICP ion source. Plasma FIB (PFIB) is demonstrated to be a feasible tool for TSV plating void metrology.
3D IC integration employs advanced interconnect technologies including through-silicon vias (TSVs), bonding, wafer
thinning, backside processing and fine pitch multi-chip stacking. In 2013, Mobile Wide I/O DRAM is expected to be
one of the first high volume 3D IC applications. Many of the manufacturing steps in TSV processing and 3D integration
can complicate inspection and metrology. This paper reviews a typical via-mid flow emphasizing the inspection and
metrology challenges inherent in 3D integration. A preliminary look at the 2011 ITRS roadmap for 3D interconnect
metrology is presented, including the gaps in currently available inspection and metrology tools.
Laboratory-based X-ray microscopy combined with computational tomography imaging is demonstrated to have
advantages over other methods of inspecting through-silicon vias (TSVs). We show that the 8 keV X-rays used by Nano
X-ray Computed Tomography (NanoXCT<sup>TM</sup>) are capable of imaging voids inside filled vias before and after annealing
without cross-sectioning the TSV. A series of - TSV arrays filled conformally and from the bottom up were inspected
by the X-ray microscope before and after annealing. Pre-existing voids in the seamline were observed in conformally
filled TSVs before annealing, while bottom up-filled TSVs do not have a seamline or voids. The same TSV samples
were repeatedly annealed at 225<sup>o</sup>C, and 300<sup>o</sup>C. After annealing, the X-ray micrograph of the same TSV array showed
void growth in only the conformally filled TSV. In addition, X-ray measurements show the total volume of void growth
increased with annealing temperature.
Through-focus scanning optical microscopy (TSOM) is a new metrology method that achieves 3D nanoscale
measurement sensitivity using conventional optical microscopes; measurement sensitivities are comparable to what is
typical when using scatterometry, scanning electron microscopy (SEM), and atomic force microscopy (AFM). TSOM
can be used in both reflection and transmission modes and is applicable to a variety of target materials and shapes.
Nanometrology applications that have been demonstrated by experiments or simulations include defect analysis,
inspection and process control; critical dimension, photomask, overlay, nanoparticle, thin film, and 3D interconnect
metrologies; line-edge roughness measurements; and nanoscale movements of parts in MEMS/NEMS. Industries that
could benefit include semiconductor, data storage, photonics, biotechnology, and nanomanufacturing. TSOM is
relatively simple and inexpensive, has a high throughput, and provides nanoscale sensitivity for 3D measurements with
potentially significant savings and yield improvements in manufacturing.
Microscopy of 3D interconnect structures is challenged by the opaque nature of silicon. Infrared (IR) microscopy
provides a way of "looking" through silicon where microscopes based on visible wavelengths fail. Perhaps the most
prevalent application of IR microscopes in 3D manufacturing is imaging sub-surface features at the interface of a bonded
wafer pair. The ability to see through silicon using IR microscopes enables a variety of metrology techniques, including
the overlay of circuit layers (e.g., metal 2 to via). IR microscopy is a non-destructive technique and, as such, it is an
ideal candidate for in-line metrology for the bonded wafer pairs required for 3D interconnects.
This paper reviews overlay metrology capability for an IR microscope. The ability to measure the overlay of bonded
wafer pairs according to the 2009 International Technology Roadmap for Semiconductors (ITRS) is demonstrated.
Overlay tolerances for a variety of copper interconnect test structures is predicted based on electrical designs, and overlay results are compared to electrical test results. The use of IR microscopy as an early indicator of electrical yield is clearly demonstrated.
This paper describes our initial investigation into building a greater understanding of the complex mechanism occurring during extreme ultraviolet (EUV) exposure of resist materials. In particular, we are focusing on the number and energy of photoelectrons generated and available for reaction with photoacid generators (PAGs). We propose that this approach will best enable the industry to develop resists capable of meeting resolution, line width roughness (LWR), and sensitivity requirements.
Base titration methods are used to determine C-parameters for three industrial EUV photoresist platforms (EUV-
2D, MET-2D, XP5496) and twenty academic EUV photoresist platforms. X-ray reflectometry is used to measure the
density of these resists, and leads to the determination of absorbance and film quantum yields (FQY). Ultrahigh levels
of PAG show divergent mechanisms for production of photoacids beyond PAG concentrations of 0.35 moles/liter. The
FQY of sulfonium PAGs level off, whereas resists prepared with iodonium PAG show FQYs that increase beyond PAG
concentrations of 0.35 moles/liter, reaching record highs of 8-13 acids generated/EUV photons absorbed.
The availability of photoresists meeting simultaneous resolution, sensitivity, and line edge roughness performance is a critical challenge for the acceptance of Extreme Ultraviolet Lithography. The Extreme Ultraviolet Resist Test Center (EUV RTC) at SEMATECH-North at the State University of New York at Albany is a state of the art facility to support the development of photoresists for EUV lithography. The facility was opened on September 28, 2005, for customer use. SEMATECH researchers, member companies, resist suppliers, and researchers from universities and institutes worldwide can use this neutral site for EUV resist development. The heart of the EUV RTC is an Exitech 5X EUV microstepper with a 0.3 numerical aperture (NA) lens. This tool has successfully imaged 45 nm dense lines in photoresists, and the ultimate imaging performance of the microstepper based on optics and wavefront quality should be near 25nm dense lines.
An Electric-field (E-field) exposure tool for Photomasks was designed, assembled, then utilized to subject 250 nanometer technology node reticles to variable electric fields. A similar study had been demonstrated using the Canary Reticle. The goal was to induce an Electrostatic Discharge (ESD), and attempt to damage the reticle's chrome structures via the Field Induced Damage Model. Electrostatic Discharge emits a radio wave in the 100 MHz to 2.0 GHz frequency range, which can be detected using a Digital Sampling Oscilloscope and antenna. Once detected via radio wave sampling techniques, the Field Induced Damage is evaluated on a KLA STARlight inspection tool, and a damage map provided. A Digital Instruments Atomic Force Microscope utilizes the damage map to locate defects for further evaluation.
An evaluation of a Photolithography Mask damaged by Electrostatic Discharge (ESD) is presented, using pictures and data from the toolset at International SEMATECH's Advanced Technology Development Facility. The Photomask used in the printability evaluation is the Canary (DuPont TM) Reticle, demonstrating various degrees of ESD-induced damage to a repeating structure contained in the chrome-on-quartz pattern. Levels of damage to the chrome structures vary from non-existent, to barely detectable, to moderate, to catastrophic. The ESD-induced damage is then measured and compared through an assortment of Mask Metrology tools.