Multi-beam mask writers (MBMW) manufactured by IMS Nanofabrication have been increasingly been accepted into mainstream mask making. Over the past decade, this new class of tools has successfully transitioned from the concept, to development and finally to the production phase. Significant technical challenges specific to the architecture were encountered and overcome. Many of these challenges are related to the large image size used by this writer. In this paper, we will review the motivation to develop this new class of writers and the key technical challenges which had to be overcome to realize lithographic promise. Current status and future opportunities to improve the architecture will be discussed.
Mask patterning capability continues to be a key enabler for wafer patterning. Mask writer performance is critical to meet reticle resolution, critical dimension uniformity, registration, and throughput requirements. Technology trends indicate that mask requirements will require higher dose resists with more complex designs producing write time growth that significantly exceeds Moore’s law estimates. Sub 10 nm technology node requirements may exceed what is practically or economically achievable using conventional single beam writers. This is driving the need to explore alternative e-beam mask writer architectures for future nodes.
Several equipment suppliers are proposing new architectures for mask patterning. These approaches share the characteristic of some level of parallelism to solve the throughput challenge caused by increasing mask pattern complexity. Although parallelism is a proven approach in laser mask writers, it has not been integrated into an e-beam platform. All of the approaches for multibeam e-beam architectures have unique technical difficulties. In some cases, suppliers have produced proof of concept results to demonstrate the feasibility of their approach and address key technical risks. Although these results are encouraging, it is clear that they need more time and industry assistance to produce a commercially worthy mask writer.
Key drivers will be considered. Proposed evolutionary extensions of the current architecture will be evaluated. The need for revolutionary architectures to satisfy future mask patterning will be explored.
Aggressive 193nm optical lithography solutions have in turn led to increasingly complex model-based OPC methodologies. This complexity married with the inevitable march of Moore's Law has produced a figure count explosion at the mask writer level. Variable shaped beam equipment manufacturers have tried to mollify the impact of this figure count explosion on the write time by the introduction of new technologies such as increased beam current density, faster DAC amplifiers and more efficient stage algorithms. Despite these efforts, mask manufacturers continue to explore ways of increasing writer throughput and available capacity. This study models the impact of further improvements in beam current density and settling times. Furthermore, this model will be used to prescribe the necessary improvement rates needed to keep pace with the shot count trends extending beyond the 45nm node.