Rotation of structures fabricated by planar processing into out-of-plane orientations can be used to greatly increase
the 3-dimensionality of microstructures. Previously this has been achieved by a self-assembly process based on surface
tension in meltable hinges. An important application is in fabricating vertical inductors on silicon, to reduce the substrate
coupling and thus increase quality factor and self-resonance frequency. Previous processes have used copper tracks, and
Pb-Sn hinges. However, the use of Cu limits potential applications because of oxidation, since the final structure is not
embedded. Moreover, a substitute hinge material is also required, as a result of legislative restrictions on Pb use. In this
paper, Au is used as an alternative to Cu for the fabrication of self-assembled 3D inductors. A process has been
developed to overcome photoresist deterioration problems due to the alkaline nature of Au electro-deposition solutions.
Furthermore, pure Sn is used instead of Pb-Sn as the hinge material. A Ni metal layer is introduced between the Au coils
and the Sn hinge to prevent inter-diffusion and formation of eutectic Au-Sn compounds. Finally a gold capping
technique is proposed to protect the Sn hinge from oxidation during hinge reflow. The fabrication techniques developed
here are compatible with post-processing on active CMOS circuits, and can be adopted for other MEMS applications.
Multi-project-wafer (MPW) services provide an economical route for prototyping of new electronic circuit designs.
However, addition of MEMS functionality to MPW circuits by post-processing (also known as MEMS-last processing) is
difficult and inefficient because MPW typically yields individual dies. One solution to this problem is to embed the
MPW dies in a carrier wafer prior to MEMS processing. We have developed a process which allows 300 μm-thick
CMOS dies to be embedded in a BSOI (bonded silicon-on-insulator) carrier prior to low-temperature processing for
integration of metal MEMS. Deep reactive ion etching (DRIE) with an STS Multiplex ICP etcher is used to form
cavities in the device layer of a BSOI wafer. By adjusting the passivation and etching cycles, the DRIE process has been
optimized to produce near-vertical sidewalls when stopping on the buried oxide layer. The cavity sizes are closely
matched to the die dimensions to ensure placement of the dies to within ±15 μm. Dies are placed in all the cavities, and
then a photoresist layer is deposited by spin-coating and patterned to provide access to the required IC contact pads. The
photoresist has the dual role of securing the dies and also planarizing the top surface of the carrier. After an appropriate
baking cycle this layer provides a suitable base for multi-level electroplating or other low-temperature MEMS