Micromirrors are a typical example of Micro-Electromechanical Systems (MEMS) with many applications including
optical scanners, optical switching, projection displays, etc. We have succeeded in producing MEMS micromirrors in a
SiGe structural layer, which can be used to realize CMOS-integrated MEMS structures. Several pixel designs were
simulated using COMSOL multiphysics and subsequently verified in hardware. They differ in mirror size, hinge length
and number of attracting electrodes (two or four). One particular mirror design enables variable Pulse Width Modulation
(PWM) addressing. In this design, the mirror switches between two extreme states with a variable duty cycle determined
by two generic high voltage signals and two CMOS-compatible pixel-specific DC voltages applied to the four attracting
electrodes. The processed arrays were subjected to Laser Doppler Vibrometer (LDV) measurements in order to verify the
simulation results. The simulated and measured pull-in voltages are compared for 8, 10 and 15μm mirrors. The
agreement between simulation and measurement lies within the expectations, which is an encouraging result for future
This paper describes how a standard laser-Doppler vibrometer (LDV) system was modified and extended for long-term
reliability measurements on micro-electromechanical (MEMS) devices. Since scanning LDV measurements are
performed by successively pointing a laser beam at a predefined set of locations, it is of the utmost importance that no
movement of the MEMS device relative to the laser source occurs during the extended lifetime testing period. In the
proposed system, the inevitable drift is compensated in three dimensions. The Z-drift is compensated by a piezo-actuated
lens and an autofocus algorithm. The in-plane drift is detected using an image correlation technique, and the coordinate
system of the LDV tool is modified accordingly. In this manner the scan points of the LDV can track the drift of the
MEMS device. During a 400-hour testing period, measurements were performed every 15 minutes. A total in-plane drift
of about 30μm was observed. The tracking error was below the resolving power of the microscope.
This paper presents two distinct measurement systems that were custom-built for the parametric and functional yield
inspection of MEMS devices on wafer-level. Throughput as well as accuracy was optimized by using automatic feature
detection and data segmentation algorithms. Inaccuracies in stage positioning during scanning are compensated for by a
grid detection algorithm. The analysis of the measurement data is performed in parallel with the ongoing measurements.
The data analysis includes the detection, parameter extraction, analysis of failures or damage of a single device and the
final stitching of the results in order to obtain a visual mapping of the measured arrays. The performance of both systems
has been demonstrated using arrays of micromirrors as test vehicles.
Fabrication of surface-micromachined structures by a post-processing module above standard IC circuits is an efficient way to produce monolithic microsystems, allowing nearly independent optimization of the circuitry and the MEMS process. However, until now the high-temperature steps needed for deposition of poly-Si have limited its application. SiGeM explores the possibilities offered by the low-temperature (450°C) deposition and structuring of poly-SiGe layers, which is compatible with the temperature budget of fully-processed standard IC wafers. In the SiGeM project several low-temperature deposition methods (CVD, PECVD, LPCVD) were developed, and were evaluated with respect to growth rate and material quality. The interconnection technology to the underlying CMOS circuitry was also developed. The capabilities of this new integration technology will be demonstrated in a monolithic high-performance rate-of-turn sensor, currently considered the most demanding MEMs application in terms of material properties of the structural layer (thickness > 10mm, stress gradient < 0.3MPa/mm) and signal processing circuitry (capacitance resolution in the aF range, SNR > 110 dB). System partitioning will combine analog and DSP circuit techniques to maximize resolution and stability. Parasitic electrical coupling within different parts of the system has been analyzed, and countermeasures to reduce it have been incorporated in the design. The feasibility of the approach has already been proved by preliminary characterization of working prototypes containing released microstructures deposited on top of preamplifier circuits built on a 0.35mm, 5-metal, 2-poly, standard CMOS process from Philips Semiconductors. Resonance frequencies are in good agreement with predictions, and quality factors above 8000 have been obtained at pressures of 0.8 mTorr. Measured SNR confirms the capability to achieve a resolution of 0.015°/s over a bandwidth of 50 Hz.
Zero-level packaging, i.e. the encapsulation of the MEMS device at wafer level, is an essential technique for MEMS miniaturization and cost reduction. A large number of different capping and sealing materials and techniques can be used. However, the testing and qualification of this type of packaging of MEMS devices requires special techniques. A number of conventional and new characterization techniques for mechanical and hermeticity testing are presented, as well as an overview about outgasing measurements and reliability testing.
The effect of the deposition parameters and Ge content on the stress gradient in poly-SiGe films was investigated. The films, ranging in thickness from 1.2 to 2.3 μm, were deposited by chemical vapor deposition (CVD) at 450 °C and plasma enhanced chemical vapor deposition (PECVD) at 520 °C. The Ge content was varied between 45 and 64 at%. Xray diffraction revealed that both PECVD and CVD films were polycrystalline. The stress gradient was determined by
measuring the deflection of 1 mm long released cantilevers. The stress gradient was found to decrease with increasing Ge content. A CVD film with 55 at% Ge was thinned using a very low power SF6/O2 plasma. The stress gradient was measured as a function of film thickness. The stress profile was calculated by matching the bending moment of the calculated profile to the bending moment obtained from the measured stress gradient. The largest change in stress occurs right at the thin film/substrate interface. PECVD films were found to possess a lower stress gradient compared to CVD films with similar thickness. This was explained by differences in TEM microstructure: CVD films have more Vshaped grains, while PECVD films have more columnar grains.
The ability of various deposition processes and materials to fill and planarize topographical features (trenches deeper than 10 micrometers ) is investigated in this work. Three different deposition processes are considered: LPCVD (Ge), PECVD (Ge, Si3N4, SiO2) and spin coating (BCB, resist, polyimide). Comparing LPCVD and PECVD processes show that, for the same trench width, thick PECVD layers can close off trenches from the top, while thick LPCVD layers fill the trenches completely. The use of PECVD layers is thus advantageous for sealing applications, where a low bottom step coverage is desired. LPCVD layers on the other hand are very useful for planarization purposes where a low ratio between the deposited film thickness and the planarized trench width is desired. Also the deposition of polymers by spin coating yields excellent planarization results with a simpler process and lower thermal budget compared to LPCVD processes. All polymers investigated fill the trenches totally. If these planarization layers are used as sacrificial layers, they should be etched isotropically and selectively with respect to the structural layer. Ge can be etched in oxidizing solutions (H2O2/H2O) and the sacrificial etch of Ge is selective towards Si, SiO2 and many other layers. SiO2 can be removed by wet or vapor HF, and resist, polyimide and BCB can be removed by O2 or O2/SF6 plasma. Which layer should be used depends on the trench fill requirements, the thermal budget and the further processing needed.
In this work the etching of different Si-oxide, Si-nitride and metal layers in HF:H2O 24.5:75.5, BHF:glycerol 2:1 and vapor HF is studied and compared. The vapor HF etching is done in a commercially available system for wafer cleaning, that was adapted according to custom specifications to enable stiction-free surface micro- machining. The etch rates as a function of etching method, time and temperature are determined. Moreover, the influence of internal and external parameters on the HF vapor etching process are analyzed before choosing the standard HF vapor etch technique used for comparing the etching behavior of the different films.
We present a new material for highly resistive heaters: thin Ti/TiN layers. Their resistivity is indeed comparable to the resistivity of NiCr, i.e. 50-100 micro-Ohn-cm. However, as opposed to the latter material, Ti/TiN is CMOS compatible and thus easier to incorporate in CMOS integrated MEMS processing. To test the reliability of thin Ti/TiN resistive heaters, both 5 nm Ti/30 nm TiN and 5 nm Ti/60 nm TiN heaters were fabricated. A thermal analysis shows a small temperature coefficient of resistivity. To test the reliability of such heaters at temperatures up to 300 degrees C, 1 micron wide Ti/TiN lines were biased using high currents. Both DC and pulsed DC current stressing resulted in very small deviations from the initial resistance for sintered and passivated heaters. The temperature uniformity over the heater line is investigated using Emission Microscopy.