A novel and simple circuit implementation of trap centres in GaAs and GaN HEMTs, MESFETs and HFETs is presented.
When included in transistor models it explains the potential-dependent time constants seen in the circuit manifestations of
charge trapping, being gate lag and drain overshoot. The implementation is suitable for both time- and harmonic-domain
simulations. The trap-centre model is based on Shockley-Read-Hall (SRH)1 statistics of the trapping process. It also
accommodates carrier injection from other important device effects, such as impact ionization and light sensitivity.
In the model, the ionization charge of the trap centre is represented by the charge in a capacitor. The potential across the
capacitor is proportional to the potential across the region of the trap centre in the semiconductor. It is positive or negative
depending on the polarity of the ionization charge - electrons or holes. When included in a transistor model, this potential
is added to the gate potential that controls the drain-current description.
The capacitor is charged or discharged by two opposing currents that are functions of the ionization potential and
temperature: one models charge emission; and the other, which is also controlled by an external potential and injected
current, models charge capture. The external potential is typically a linear function of a transistor's terminal potentials.
The injection current can model charge generated by light or by holes from impact ionization.
The four parameters for the model are simply the signed potential of the trap centre when fully ionized, the time
constant for charge emission at a specific temperature, the injection-current sensitivity, and the activation energy of the
emission process. The latter is used to predict the temperature dependence of the emission rate. The capture rate is
determined within the model by an exponential function of the external potential that controls capture. Thus the model
elegantly predicts asymmetry between trap charging and discharging rates. The model accounts for variation in emission
and capture rates with temperature, which is shown to vary significantly over typical transistor operating ranges.
The evolution of wide-bandgap semiconductor transistor technology is placed in historical context with other
active device technologies. The relative rapidity of GaN transistor development is noted and is attributed to
the great parallel activity in the lighting sector and the historical experience and business model from the III-V
compound semiconductor sector. The physical performance expectations for wide-bandgap technologies such
as Gallium-Nitride Field-Effect Transistors (GaN FETs) are reviewed. We present some device characteristics.
Challenges met in characterising, and prospects for modeling GaN FETs are described. Reliability is identified
as the final remaining hurdle facing would-be foundries. Evolutionary and unsurprising applications as well as
novel and revolutionary applications are suggested. Novel applications include wholly monolithic switchmode
power supplies, simplified tools for ablation and diathermy in tissue, and very wide dynamic range circuits for
audio or low phase noise signal generation. We conclude that now is the time to embark on circuit design of MMICs in wide-bandgap technology. The potential for fabless design groups to capitalise upon design IP without strong geopraphic advantage is noted.
For integrated circuit design up to 50GHz and beyond accurate models of the transistor access structures and intrinsic
structures are necessary for prediction of circuit performance. The circuit design process relies on optimising transistor
geometry parameters such as unit gate width, number of gates, number of vias and gate-to-gate spacing. So the relationship
between electrical and thermal parasitic components in transistor access structures, and transistor geometry is important to
understand when developing models for transistors of differing geometries. Current approaches to describing the geometric
dependence of models are limited to empirical methods which only describe a finite set of geometries and only include
unit gate width and number of gates as variables. A better understanding of the geometric dependence is seen as a way
to provide scalable models that remain accurate for continuous variation of all geometric parameters. Understanding the
distribution of parasitic elements between the manifold, the terminal fingers, and the reference plane discontinuities is an
issue identified as important in this regard. Examination of dc characteristics and thermal images indicates that gate-to-gate
thermal coupling and increased thermal conductance at the gate ends, affects the device total thermal conductance. Consequently, a distributed thermal model is proposed which accounts for these effects. This work is seen as a starting point for developing comprehensive scalable models that will allow RF circuit designers to optimise circuit performance parameters such as total die area, maximum output power, power-added-efficiency (PAE) and channel temperature/lifetime.
This work investigates the nature of the nonlinearities in an anti-parallel combination of Schottky diodes, which
is often used as a frequency converting device or a mixer. An anti-parallel Schottky diode pair mixer requires
only half the local oscillator frequency. The mixing terms of utmost importance are, the wanted fundamental
frequency converted product, the unwanted third-order frequency converted product and the breakthrough of
the local oscillator signal. This work aims to discover how the nonlinearities inside the mixer can affect the
generation of unwanted products. Frequency upconversion measurements of an anti-parallel diode pair mixer,
fabricated on WIN semiconductor's 0.15μm low-noise process have been used to extract a polynomial model
of the mixer nonlinearities. The polynomial function representing nonlinear resistance contains only odd-power
terms and a second polynomial function encapsulating capacitance and its asymmetry comprises of both even
and odd-power terms. The coefficients of the model are extracted by fitting to measured amplitudes of the
third-order mixing products and the local oscillator breakthrough over a range of the local oscillator drive
powers, commonly encountered in practise. The model so extracted is validated by comparing its predictions
with measured amplitudes of wanted and unwanted frequency products, as functions of local oscillator power
at various local oscillator frequencies. The form of the polynomial model indicates the dominance of nonlinear
resistance in the generation of the unwanted third-order mixing products. It also points to asymmetry of the
capacitance-voltage characteristic as a possible reason behind unwanted local oscillator breakthrough in anti-parallel
diode pair mixers.
This paper investigates up/down conversion asymmetry in intermodulation distortion observed in measurements
of resistive FET mixers. Symmetric behaviour is intuitively expected of such a topology, so a first principle
analysis is carried out to determine the responsible mechanism.
Previous analysis of up/down conversion asymmetry has focused on conversion gain in diode based mixers,
whereas the effects investigated in this paper are for mixers with symmetry in this aspect. The aim is to fully
understand the intermodulation mechanism, so that performance can be enhanced.
The approach taken is to consider the mixer as a two-port nonlinear element driven by multiple frequency
sources. Mixing performance then becomes a function of the relative frequencies and amplitudes, which is
related to the mode of operation as an up or down converter. This investigation is performed with FET models
of increasing complexity and physical accuracy. In this manner the effect on intermodulation and other mixer
performance parameters can be isolated to those differences introduced with each model change such as the effect
of adding higher order even/odd terms to the drain or gate non-linear model independently.
The result is an understanding into the FET properties that contribute to intermodulation distortion. This
knowledge is useful to designers as it allows educated modifications to mixer topology to obtain improved linearity.
Results also give the ability to minimize the asymmetry, reducing the design cost involved in producing a separate
solution for each mode. These results can also be used to guide modification of the physical structure of a FET for mixer applications.
Field Effect Transistors exhibit a variety of complicated dynamic and nonlinear interactions that affect millimetre-wave
devices used for telecommunications. The dynamics include self heating, bias dependent change in trapped charge, and
variations due to impact ionization. These are feedback mechanisms that contribute to intermodulation as a memory effect does. A FET is better viewed as a nonlinear system with feedback, bias dependent rates, and high-order nonlinear conductance and charge storage with specific terminal to terminal interaction. Identifying and characterizing FET dynamics and linearity is a key step in the design process. Extraction of true intrinsic characteristics is an important first step to understanding the physics of trapping and heating within the device. Standard measurement techniques tend to derive access networks with an emphasis on scaling with layout geometry. The intrinsic device is then modelled as whatever is left after de-embedding the measurements. As such, the intrinsic model exhibits significant frequency dispersions and behaviour that is not easily related to the operation of the transistor. A correct determination of the access network reveals that the dispersions within the intrinsic data are related to physical process, such as heating and trapping. Recent work has been carried out to accurately implement trapping within a circuit simulator. This is key to correct prediction of intermodulation and bias dependence effects generated by a FET. It is shown that heating significantly affects
trapping and is an important factor in the transient rate dependence of the characteristics. The implementation of trapping
within a circuit model, and its consequences on linearity are explored.
KEYWORDS: Photomicroscopy, Oscillators, Receivers, Linear filtering, Bandpass filters, Logic, VHF band, Signal detection, Sensors, Digital signal processing
High speed frequency dividers are critical parts of frequency synthesisers in wireless systems. These dividers
allow the output frequency from a voltage controlled oscillator to be compared with a much lower external
reference frequency that is commonly used in these synthesisers. Common trade-offs in high frequency dividers
are speed of division, power consumption, real estate area, and output signal dynamic range. In this paper
we demonstrate the design of a high frequency, low power divider in 0.18 µm SiGe BiCMOS technology. Three
dividers are presented, which are a regenerative divider, a master-slave divider, and a combination of regenerative
and master-slave dividers to perform a divide-by-8 chain. The dividers are used as part of a 60 GHz frequency
synthesizer. The simulation results are in agreement with measured performance of the regenerative divider.
At 48 GHz the divider consumes 18 mW from a 1.8 V supply voltage. The master-slave divider operates up to
36 GHz from a very low supply voltage, 1.8 V. The divide-by-8 operates successfully from 40 GHz to 50 GHz.
Some aspects of microwave transistor behavior are emerging as significant factors in applications involving increasing signal bandwidths, increasing carrier frequencies, and modulation schemes requiring high linearity. The design of circuits for these applications cannot rely on narrow-band, low frequency, or small-signal assumptions. Instead, a full spectral view of the frequency-dependent high-order nonlinearity of transistors needs to be considered. A paramount performance issue is intermodulation, which is significantly affected by circuit and device properties at base-band frequencies. Any variation in device or circuit behavior that responds to low frequencies is also excited by comparable differences between the frequencies of signal components. An exploration of the dependence of nonlinearity on signal spectra demonstrates the need to consider transistor behavior over all frequencies. To do this for the design of circuits and selection of device technology, accurate models of heating and charge trapping are essential. These require distributed network or sub-first order filters to model them because they impact an extremely large range of frequencies, from dc to many Gigahertz. The behavior of transistors varies with frequency and operating condition. This presents a measurement and characterization issue, which pulse testing coupled with alternative interpretation of RF data can ameliorate. A large-signal model should include trapping and heating and descriptions of nonlinearity that are continuous and consistent with small-signal behavior. The determination of trapping behavior in a closed-form description and its complete characterization are still a challenge.
Traps at the surface of devices cause gate lag, which is the delayed response of drain current to a step change of gate voltage. The effect of gate lag limits the performance of devices and integrated circuits such as digital circuits, digital radio systems. The manifestation of gate lag in the frequency domain is transconductance and drain conductance dispersion. Gate lag is usually caused by surface hole trapping. Traps at the surface are charged negatively during turn-off of the devices. The negative charge turns the device further off. After turnon, these negative charges decay by means of capturing holes, which turns the device further on. The finite time related to trap charging and discharging results in gate lag. Pulsed measurements have been carried out to observe and measure this current lag in HEMT devices. Drain voltage has been found to have significant effect on the time constant of carrier trapping. Prior knowledge of the lag enables one to modify the design and selecting proper bias point for a specific application. For this purpose, a SPICE model has been developed to simulate gate lag in devices. The time lag is modelled by an RC time constant. Depending on the drain voltage, this time constant changes from 10ms to 1us. The model also predicts the transient gate current for gate voltage going down towards pinch-off. The model has further been tested for near half the saturated drain current. Two-tone intermodulation simulation is being investigated with the model.
The use of GaAs high electron mobility transistors (HEMTs) in monolithic microwave integrated circuits (MMICs) presents significant challenges to modelling intermodulation distortion performance. It is important that the distortion can be accurately simulated, to avoid the cost of prototyping MMICs and to meet the increasingly stringent low distortion requirements of modern communication system standards. This necessitates the careful consideration of the method used to characterise and extract models from HEMTs. The challenge is to provide a high-order nonlinear model that is accurate over a full spectrum of frequencies. This paper presents measurements of the complicated behavior of HEMT devices. Third-order distortion is seen to sometimes depend on higher-order nonlinearity. In addition, the HEMTs exhibit dispersion in their drain current characteristics up to GHz frequencies due to anomalous effects such as semiconductor charge trapping. Methods to characterise HEMTs are discussed and their applicability is pointed out. In particular, a characterisation method for HEMTs should be able to extract nonlinearities up to a sufficiently high order for the required application, and thus should have high dynamic range. In addition to magnitude, it should be able to measure phase information. It is important that the measurements can be performed at frequencies higher than those affected by dispersion, and high enough that device reactive nonlinearities can be measured. The HEMTs are characterised using a number of methods to show the importance of these considerations.
This paper looks at the problems associated with pulsed testing of GaN and GaAs HEMTs and its use in examining the charging and discharging times of the various traps that affect conduction. A particular problem is that the RF behaviour of these transistors varies with the state of charge of the traps. This is a concern for a large class of applications where the usage pattern is comparable to the time constants of the traps. Such classes include the intermittently-switched front ends of 802.11 and mobile telephone circuits. The conventional approach with pulsed testing is to sit at a bias point for a sufficiently long time and then to pulse to characteristic voltages very quickly before returning to the bias. If the pulsing to the applied characteristic voltages is much faster than the time constants of the traps of the transistor, then the characteristic measured will reflect the state of charge of the traps for the bias point. Our approach here is to perform a series of characteristic measurements as the bias and trap charge-state change. Each characteristic is measured too quickly to affect the trapped charge significantly. The set of characteristics then reflects the changing nature of the transistor's bias and state of charge of its traps.
The significance of the nonlinearity of HEMT capacitance models to the prediction of intermodulation is investigated. Three capacitance models, one linear and two with contrasting nonlinear behavior, are shown to exhibited almost identical performance. It is concluded that the nonlinearity of the low-frequency model is the dominant distortion generating component. Development of capacitance models with accurate high-order derivatives is unwarranted without an accurate dc model. Therefore, careful characterization of the drain current description is most important for successful circuit simulation.
Laser-assisted repair of nerves is often unsatisfactory and has a high failure rate. Two disadvantages of laser assisted procedures are low initial strength of the resulting anastomosis and thermal damage of tissue by laser heating. Temporary or permanent stay sutures are used and fluid solders have been proposed to increase the strength of the repair. These techniques, however, have their own disadvantages including foreign body reaction and difficulty of application. To address these problems solid protein solder strips have been developed for use in conjunction with a diode laser for nerve anastomosis. The protein helps to supplement the bond, especially in the acute healing phase up to five days post- operative. Indocyanine green dye is added to the protein solder to absorb a laser wavelength (approximately 800 nm) that is poorly absorbed by water and other bodily tissues. This reduces the collateral thermal damage typically associated with other laser techniques. An investigation of the feasibility of the laser-solder repair technique in terms of required laser irradiance, tensile strength of the repair, and solder and tissue temperature is reported here. The tensile strength of repaired nerves rose steadily with laser irradiance reaching a maximum of 105 plus or minus 10 N.cm-2 at 12.7 W.cm-2. When higher laser irradiances were used the tensile strength of the resulting bonds dropped. Histopathological analysis of the laser- soldered nerves, conducted immediately after surgery, showed the solder to have adhered well to the perineurial membrane, with minimal damage to the inner axons of the nerve. The maximum temperature reached at the solder surface and at the solder/nerve interface, measured using a non-contact fiber optic radiometer and thermocouple respectively, also rose steadily with laser irradiance. At 12.7 W.cm-2, the temperatures reached at the surface and at the interface were 85 plus or minus 4 and 68 plus or minus 4 degrees Celsius respectively. This study demonstrates the feasibility of the laser-solder repair technique for nerve anastomosis resulting in improved tensile strength. The welding temperature required to achieve optimal tensile strength has been identified.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.