EUV lithography is likely more sensitive to drift from thermal and degradation effects than optical counterparts. We have developed an automated approach to photoresist image-based aberration metrology. The approach uses binary or phase mask targets and iterative simulation based solutions to retrieve an aberrated pupil function. It is well known that a partially coherent source both allows for the diffraction information of smaller features to be collected by the condenser system, and introduces pupil averaging. In general, smaller features are more sensitive to aberrations than larger features, so there is a trade-off between target sensitivity and printability. Therefore, metrology targets using this technique must be optimized for maximum sensitivity with each illumination system. This study examines aberration metrology target optimization and suggests an optimization scheme for use with any source. Interrogation of both low and high order aberrations is considered. High order aberration terms are interrogated using two separate fitting algorithms. While the optimized targets do show the lowest RMS error under the test conditions, a desirable RMS error is not achieved by either high order interrogation scheme. The implementation of a previously developed algorithm for image-based aberration metrology is used to support this work.
As EUV lithography attempts to outperform other lithographical methods to the sub-14 nm node, the demand for a larger NA traditionally dominates the drive for scaling. There are, however, many challenges to overcome in order to accomplish this . Due to the reflective optics in EUV systems, angular effects of oblique illumination, and non-zero chief ray angle at the objective (CRAO), must be carefully considered and will need to be well understood if high-NA EUV is to be successful. This study investigates impact on of the bias between horizontal and vertical feature CD, image placement error and NILS. Effects of sidewall absorber angle, absorption coefficient (k) and absorber thickness are observed through pitch with various source shapes in an EUV lithography system.
Historically IC (integrated circuit) device scaling has bridged the gap between technology nodes. Device size reduction
is enabled by increased pattern density, enhancing functionality and effectively reducing cost per chip. Exemplifying
this trend are aggressive reductions in memory cell sizes that have resulted in systems with diminishing area between
bit/word lines. This affords an even greater challenge in the patterning of contact level features that are inherently
difficult to resolve because of their relatively small area and complex aerial image. To accommodate these trends,
semiconductor device design has shifted toward the implementation of elliptical contact features. This empowers
designers to maximize the use of free device space, preserving contact area and effectively reducing the via dimension
just along a single axis. It is therefore critical to provide methods that enhance the resolving capacity of varying aspect
ratio vias for implementation in electronic design systems. Vortex masks, characterized by their helically induced
propagation of light and consequent dark core, afford great potential for the patterning of such features when coupled
with a high resolution negative tone resist system. This study investigates the integration of a vortex mask in a 193nm
immersion (193i) lithography system and qualifies its ability to augment aspect ratio through feature density using aerial
image vector simulation. It was found that vortex fabricated vias provide a distinct resolution advantage over
traditionally patterned contact features employing a 6% attenuated phase shift mask (APM). 1:1 features were
resolvable at 110nm pitch with a 38nm critical dimension (CD) and 110nm depth of focus (DOF) at 10% exposure
latitude (EL). Furthermore, iterative source-mask optimization was executed as means to augment aspect ratio. By
employing mask asymmetries and directionally biased sources aspect ratios ranging between 1:1 and 2:1 were
achievable, however, this range is ultimately dictated by pitch employed.
We continue to study the feasibility of using Directed Self Assembly (DSA) in extending optical lithography for High
Volume Manufacturing (HVM). We built test masks based on the mask datatprep flow we proposed in our prior year’s
publication . Experimental data on circuit-relevant fin and via patterns based on 193nm graphoepitaxial DSA are
demonstrated on 300mm wafers. With this computational lithography (CL) flow we further investigate the basic
requirements for full-field capable DSA lithography. The first issue is on DSA-specific defects which can be either
random defects due to material properties or the systematic DSA defects that are mainly induced by the variations of the
guiding patterns (GP) in 3 dimensions. We focus in studying the latter one. The second issue is the availability of fast
DSA models to meet the full-chip capability requirements in different CL component’s need. We further developed
different model formulations that constitute the whole spectrum of models in the DSA CL flow. In addition to the
Molecular Dynamic/Monte Carlo (MD/MC) model and the compact models we discussed before , we implement a 2D
phenomenological phase field model by solving the Cahn-Hilliard type of equation that provide a model that is more
predictive than compact model but much faster then the physics-based MC model. However simplifying the model might
lose the accuracy in prediction especially in the z direction so a critical question emerged: Can a 2D model be useful fro
full field? Using 2D and 3D simulations on a few typical constructs we illustrate that a combination of 2D mode with
pre-characterized 3D litho metrics might be able to approximate the prediction of 3D models to satisfy the full chip
runtime requirement. Finally we conclude with the special attentions we have to pay in the implementation of 193nm
based lithography process using DSA.
The first fully integrated SOI device using 42nm-pitch directed self-assembly (DSA) process for fin formation has been demonstrated in a 300mm pilot line environment. Two major issues were observed and resolved in the fin formation process. The cause of the issues and process optimization are discussed. The DSA device shows comparable yield with slight short channel degradation which is a result of a large fin CD when compared to the devices made by baseline process. LER/LWR analysis through the DSA process implied that the 42nm-pitch DSA process may not have reached the thermodynamic equilibrium. Here, we also show preliminary results from using scatterometry to detect DSA defects before removing one of the blocks in BCP.
EUV insertion timing for High Volume Manufacturing is still an uncertainty due to source power and EUV mask infrastructure limitations. Directed Self Assembly (DSA) processes offer the promise of providing alternative ways to extend optical lithography cost-effectively for use in the 10nm node and beyond. The goal of this paper is to look into the technical prospect of DSA technology, particularly in the computational and DFM area. We have developed a prototype computational patterning toolset in-house to enable an early Design –Technology Co-Optimization to study the feasibility of using DSA in patterning semiconductor devices and circuits. From this toolset we can identify the set of DSA specific design restrictions specific to a DSA process and plan to develop a novel full chip capable computational patterning solution with DSA. We discuss the DSA Computational Lithography (CL) infrastructure using the via and fin layers as examples. Early wafer data is collected from the DSA testmask that was built using these new toolsets. Finally we discuss the DSA ecosystem requirements for enabling DSA lithography and propose how EDA vendors can play a role in making DSA Lithography (DSAL) a full-chip viable technology for multiple process layers.
The patterning capability of the directed self-assembly (DSA) of a 42nm-pitch block copolymer on
an 84nm-pitch guiding pattern was investigated in a 300mm pilot line environment. The chemoepitaxy
guiding pattern was created by the IBM Almaden approach using brush materials in
combination with an optional chemical slimming of the resist lines. Critical dimension (CD)
uniformity, line-edge/line-width roughness (LER/LWR), and lithographic process window (PW) of
the DSA process were characterized. CD rectification and LWR reduction were observed. The
chemical slimming process was found to be effective in reducing pattern collapse, hence, slightly
improving the DSA PW under over-dose conditions. However, the overall PW was found to be
smaller than without using the slimming, due to a new failure mode at under-dose region.