The buffer insertion has been a mechanism widely used to increase the performances of advanced VLSI digital circuits
and systems. The driver or repeater used to this purpose has effect on the timing characteristics on the signal on the wire,
as propagation delay, signal integrity, transition time, among others. The power concerns related to buffering have also
received much attention, because of the low power requirements of modern integrated systems. In the same way, the
buffer insertion has strong impact on the reliability of synchronous systems, since the suited distribution of clock requires
reduced or controlled clock-skew, being the buffer and wire sizing, a crucial aspect. In a different way, buffer insertion has
been also used to reduce noise generation, especially in heavily loaded nets, since the inclusion of buffers help to desynchronize
signal transitions. However, the inclusion of buffers of inverters to improve one or more of these characteristics
have often negative effect on another parameters, as it happens in the average and peak of supply current. Mainly, the
inclusion of a buffer to reduce noise (peak power), via desynchronizing transitions, could introduce more dynamic consumption,
but reducing the short-circuit current because of the increment of signal slope. Thus, the average/peak current
optimization can be considered a design trade-off. In this paper, the mechanism to obtain an average/peak power optimization
procedure are presented. Selected examples show the feasibility of minimizing switching noise with negligible
impact on average power consumption.
This paper provides a simple methodology, based on available CAD tools, able of extracting valuable information on supply
current curves, otherwise limited by the layout disposal, making it impracticable for the present high density circuits.
The approach starts at HDL level, which will be automatically synthesized to a gate level being the peak power (one peak
per clock cycle) measured at this level, giving an idea of the switching noise generated. Although an indirect method, it
provides a quantitative value of noise valid for comparison between different proposals. To assess the methodology two
different tools are used: PrimePower and NanoSim, both from Synopsys, that generate an average power and a peak
power value. We will see that NanoSim is good for noise estimation but this is not the case of PrimePower.
Full adders are one of the most important building blocks in VLSI digital arithmetic. The area, electrical, timing, power consumed and noise generated characteristics of this cell are strongly dependent on the design technique. An exhaustive work taking into account the above parameters is done, and that complete analysis will be of utility for the community of digital designers. Emphasis will be done in power/noise figures, of most important concern in current CMOS mixed-signal design. The full adders considered are those using complementary CMOS, pass-transistor logic, double pass-transistor logic, and two versions based on CMOS transmission gate. Main parameters as area, delay, power consumption and noise generation have been measured by electrical simulation in a 0.35 μ<i>m </i>CMOS technology. The main results obtained are, on one hand, the selection of a logic family for a specific application and, on the other hand, the selection of a specific full adder structure for an optimized parameter option -power, noise or speed.
One of the most important sources of switching noise in large VLSI circuits is the clock-driven circuitry, meaning that memory elements are the main source of noise in digital circuits. This paper faces the application of clock-gating, a well known low-power technique, to the reduction of switching-noise generation. Sources of switching noise in master-slave flip-flops will be analyzed. It will be shown how different solutions for the clock-gated logic show very different results regarding switching-noise generation. Illustrative examples characterized through HSPICE simulations, as well as the application of clock-gating to 16-bit synchronous counter as demonstrator, will provide useful design guidelines for reduction of switching noise generation.
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate events according to their information levels. Neurons with more information (activity, derivative of activities, contrast, motion, edges,...) generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. AER technology has been used and reported for the implementation of various type of image sensors or retinae: luminance with local agc, contrast retinae, motion retinae,... Also, there has been a proposal for realizing programmable kernel image convolution chips. Such convolution chips would contain an array of pixels that perform weighted addition of events. Once a pixel has added sufficient event contributions to reach a fixed threshold, the pixel fires an event, which is then routed out of the chip for further processing. Such convolution chips have been proposed to be implemented using pulsed current mode mixed analog and digital circuit techniques. In this paper we present a fully digital pixel implementation to perform the weighted additions and fire the events. This way, for a given technology, there is a fully digital implementation reference against which compare the mixed signal implementations. We have designed, implemented and tested a fully digital AER convolution pixel. This pixel will be used to implement a full AER convolution chip for programmable kernel image convolution processing.
Digital switching noise is the main source of on-chip noise in mixed-signal ICs. When many digital gates change state together, a large cumulative current spike flows through parasitic resistances and inductances and noise is also injected into the substrate, causing the sensitive analog portions of the design to malfunction. Many solutions have been proposed to alleviate this problem from both the analog and the digital domain. Some current mode families are used in low noise applications, but are strongly unsuited for low power applications, due to its static power consumption. In this paper we propose a set of techniques to reduce the switching noise generated by the digital circuitry, based on classical digital (static CMOS) methodologies at a circuit level. One of the most important sources of switching noise in large VLSI circuits is the clock-driven circuitry and the clock generation and distribution logic. It is well known for the mixed-signal community that harmonics of clock signal are easily injected in the analog part. This paper analyzes how some actuations like the insertion of buffers, the suited placement and routing of the clock tree cells, as well as the suited sizing of devices can save switching noise. In fact different solutions for the clocking logic generate very different results for switching noise. This paper faces the analysis and design of clock generation and distribution logic oriented towards low noise applications. Some illustrative examples will shown the feasibility of the proposed solutions, and some useful design guidelines will be proposed for the community of digital designers.
Switching noise reduction in mixed-mode VLSI circuits is of high importance in mixed-mode applications. The use of current-mode logic circuits, such as Current Steering Logic (CSL) or Current Balanced Logic (CBL) offers advantages in switching noise reduction, since their operation way is based on the use of an almost constant current source. However their usage is limited since they exhibit static power consumption. For this reason, these logic families are only used in those applications where the low-noise requirement becomes critical. Additionally, memory elements are the main source of noise in digital circuits, because they are driven for a few clock signals. In this paper, the analysis of different implementations of memory elements -edge-triggered flip-flops, in current-mode technologies is presented. Main parameters as area, delay, power consumption and noise generation have been measured by electrical simulation in a 0.35 m CMOS technology. The reliability in operation has been also quantified by timing violation parameters measurement. The main results obtained are, on one hand, the selection of a logic family for an specific application and, on the other hand, the selection of an specific flip-flop structure for a optimized parameter option -power, noise or speed. Variations of measured parameters for different operation conditions have been also considered. The novelty of this work lies in this analysis has not been considered before, being usual in other CMOS technologies.