As the semiconductor industry progresses towards the 2nm logic technology node in pursuit of improved chip performance and density, the demand for minimum pitch scaling in the back-end-of-line (BEOL) interconnect becomes crucial. Imec N3 logic design rules defined a minimum Metal 2 (M2) layer pitch of 30 nm, representing 2nm technology nodes. To further enhance semiconductor integrated circuit performance, attention is shifting towards advanced mask materials for current 0.33 NA EUV scanners. Low-n masks have been shown to improve extreme ultraviolet (EUV) imaging performance in terms of Local-CDU (LCDU), reduced mask 3D effects and improved optical contrast compared to a Tabased mask. In our study, we observed notable enhancements in optical contrast for real logic designs using a low-n mask. Our findings demonstrate an impressive LCDU of 5.5 nm and CGDU of 5.5 nm for Place’n’Route (PnR) structures at a pitch of 32. Furthermore, we successfully printed tip-to-tip (T2T) features as small as 20 nm on the wafer for regular tip-to-tip structures that didn’t get any Optical proximity Correction (OPC). These advancements mark significant progress towards manufacturability and developing a holistic patterning approach for random logic metal with EUV.
One of the key steps in the pattern formation chain of extreme ultraviolet (EUV) lithography is the development process to resolve the resist pattern after EUV exposure. The traditional development process might be insufficient to achieve the requirements of ultra-high-resolution features with low defect levels. The aim of this paper is to establish a process to achieve a good roughness, a low defectivity at a low EUV dose, and capability for extremely-high-resolution for high numerical aperture (NA) and hyper-NA EUV lithography. A new development method named ESPERT™ (Enhanced Sensitivity develoPER Technology™) has been introduced to improve the performance of metal oxide-resists (MOR). ESPERT™ as a chemical super resolution technique effectively apodized the MOR chemical image, improving chemical gradient (higher exposure latitude (EL)) and reducing scums (fewer bridge defects). This new development method can also keep the resist profile vertical to mitigate the break defects. The performances of the conventional development and ESPERT™ were evaluated and compared using 0.33 NA EUV, 0.5 NA EUV, and electron beam (EB) exposures, for all line-space (LS), contact hole (CH), and pillar (PL) patterns. Using 0.33 NA EUV scanners on LS patterns, both bridge and break defects were confirmed to be reduced for all 32-nm-pitch, 28-nm-pitch, 26-nm-pitch LS patterns while reducing the EUV dose to size (DtS). In the electrical yield (1 meter length) test of breaks/bridges of 26-nm pitch structures, ESPERT™ reduced EUV dose while its combo yield was almost 100% over a wide dose range of 20mJ/cm². For CH patterns, in the case of 32-nm-pitch AEI (after etch inspection), EL was increased 7.5% up to 22.5%, while failure free latitude (FFL) was widened from 1-nm to 4-nm. A 16-nm-pitch LS pattern was successfully printed with 0.5 NA tool, while a 16-nm-pitch PL and an 18-nm-pitch CH patterns were also achieved with an EB lithography by ESPERT™. With ESPERT™, there was no pillar collapse observed for 12-nm half-pitch PL by 0.5 NA and 8-nm half-pitch PL by EB. With all the advantages of having a high exposure sensitivity, a low defectivity, and an extremely-high-resolution capability, this advanced development method is expected be a solution for high-NA EUV towards hyper-NA EUV lithography.
High-NA EUV lithography is currently under development to keep up with device node scaling with smaller feature sizes. In this paper, the most recent advances in EUV patterning using metal oxide resists (MOR) and chemically amplified resists (CAR) are discussed. A newly developed resist development method (ESPERT™) was examined on MOR with 24 nm pitch line and space (L/S) patterns and 32 nm pitch pillars for preparation of high-NA EUV patterning. The patterning results showed improved sensitivity and pattern collapse margin. CAR contact hole patterning at 28 nm pitch was also examined by stochastic lithography simulation. The simulation results indicate that resist film thickness needs to be optimized for target pitches.
In order to improve logic via printing we propose staggered vias to effectively regularize randomly placed vias in a typical logic design. We accomplish this (i) by forcing via placement on a staggered sub-grid of the standard manhattan grid and (ii) by placing smaller fixed-size via Sub-Resolution Assist Features (SRAFs) on all remaining empty positions of the staggered grid. We devised a methodology to create such staggered via placement in a standard Place&Route (PNR) design flow and evaluated the concept on a 64-bit (64b) ARM core implementation through a PowerPerformance-Area (PPA) analysis. From a PNR run-time perspective and PPA analysis this looked a very viable implementation with little to no disadvantages compared to standard via placement. Finally, to experimentally test and compare staggered vias and against standard manhattan vias, we designed a via mask with both staggered and standard manhattan vias patterns and exposed them on an 0.33NA NXE3400 EUV lithography system. Analysis of experimental results on a 38nm via pitch show 40% smaller best-focus shift across the slit, and 20% smaller via-via CD variation for staggered vias compared to Manhattan vias with regular SMO.
As technology nodes continue to scale down, maintaining roughness and defectivity during the pattern transfer becomes more challenging. For the smallest features, Metal-Organic Resists (MOR) are preferred due to their better selectivity than Chemically Amplified Resists (CAR). However, MORs are usually negative tone resists. Primarily based on defectivity reasons, dark field Extreme Ultraviolet (EUV) masks are strongly preferred over light field EUV masks. Therefore, the MOR resist is more suited for pillar patterning than hole patterning. The purpose of this paper is to show that exposing pillars with MOR and converting them into holes can yield better roughness and defectivity than patterning holes with CAR directly. A similar comparison is done for the tone reversal of lines and spaces. It is shown that the Local Critical Dimension Uniformity (LCDU) of holes and the Line Edge Roughness (LER) of lines/spaces are well conserved throughout the tone inversion process.
The goal of this work is to prepare process readiness towards High NA EUV lithography, by using 0.33NA exposures on
NXE3400B scanner. We focus on photoresists, underlayers and etch processes mitigation of P24nm Line Space patterns.
Etch transfer has been validated for Metal Oxide Resist (MOR). Furthermore, we investigate challenges to accelerate
Chemically Amplified Resist (CAR) P24nm Line Space processes. Also, here, promising patterning results have been
achieved. Thin film metrology-friendly methods like Atomic Force Microscopy (AFM) have been performed to
characterize and improve the CAR-based etch processes.
As feature sizes continue to shrink, low k1 lithographic processes are required to advance chip technologies. To achieve actual gains in resolution, both the advances in optical systems and imaging capabilities, as well as the improvements in EUV materials and photoresists are key. Researchers today are evaluating the readiness of State-of-the-art materials and processing needed for future applications with 0.33NA exposures at the ASML-imec Advanced Patterning Center, together with studies involving High-NA exposure tools at Lawrence Berkeley National Laboratories and the Paul Scherrer Institute. This talk will give a broad overview of the progress and innovations on high resolution photoresists and patterning processes, and will highlight the key areas of development needed towards high-NA EUV lithography.
In this paper, patterning challenges that led to the fabrication of a first Spin Torque Majority Gate (STMG) device are explored. We have highlighted key process module developments from the Magnetic Tunnel Junctions (MTJs) pillar patterning to dual damascene scheme wiring module. Spin devices such as STMG have already been proposed as a replacement for conventional CMOS transistors. The main challenge to their experimental demonstration remains the successful fabrication of connected MTJs through a ferromagnetic layer, allowing spin transport across the gate. We propose a new etching approach utilizing Ion Beam Etching (IBE), to be able to pattern the MTJs with high precision and with less damage to the magnetic layers. Furthermore, we have introduced Electron-beam lithography to further scale down the device geometries. This development paves the way towards a fully integrated STMG device for Spin Logic applications.
KEYWORDS: Line width roughness, Lithography, Etching, Electron beam lithography, System on a chip, Metals, Scanning electron microscopy, Silicon, Resistance, Extreme ultraviolet
Maskless electron beam lithography is an attractive solution to address sub-90 nm technology nodes with high throughput and manufacturing costs reduction. One of the key challenges is to meet entirely process/integration specifications in terms of resolution, resist sensitivity, roughness and etch transfer into underlayers. In this paper, we evaluate and identify the optimal stack to fit printing performance using e-beam exposures and etch transfer patterning. Besides imaging performance, other key parameters such as outgassing and charge dissipation due to high current density are also considered to fully achieve targets for the machine developed by MAPPER Lithography.
KEYWORDS: Lithography, Electron beam lithography, Silicon, Point spread functions, Scanning electron microscopy, Critical dimension metrology, 3D modeling, Information technology, Etching, Monte Carlo methods
In addition to sub-20 nm technology nodes, multi-beam lithography at low-energy has also the capability to address mature CMOS technologies [130-45nm nodes] with high throughput and significant manufacturing costs reduction. It requires both “fast” resists for throughput gain and cost of ownership and “thick” resists matched with the current post-lithography processes such as etching and implant steps. We successfully demonstrated patterning of 45-130 nm nodes structures on different thick resists (up to 160 nm) with a 5 keV Mapper pre-alpha tool. In parallel, we developed a theoretical model to simulate 3D patterning showing good agreement with our experimental results.
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