In this paper, we present an innovative approach to reduce power and accelerate timing closure by using
simulated silicon-calibrated contours to predict the litho effects on transistor gates and perform litho-aware
critical paths analysis. This approach is used to filter the false hold time violations and focus designers'
actions on the most relevant violations. After silicon validation, the application of this technique to hold
time fixing on a 90nm micro-controller unit product reduces the power increase and runtime of the hold
buffer insertion. This study not only demonstrates the feasibility of the Litho-aware STA flow but also
shows its value to reduce hold time fixing effort and power dissipation caused by buffer insertion.
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