This study focused on the defect behavior analysis with CD variation on EUV via hole pattern using photolithographic process and etch transfer performance. While defect requirements are not as stringent for memory devices, logic devices must be defect-free. Currently, a defect which comes from the process or material can only be detected by top-down inspection approach, however, it is difficult to detect killer defect types such as incompletely opened holes. To develop 5- nm logic node, a hole pattern 15 nm or smaller is required. Identification of failure at the bottom of the hole becomes more challenging. Nevertheless, the process window margin by the amount of dose/focus is not fully explored to find the defect occurrence tendency. So far, there are reported analyses on the scaling of pattern and pitches. In this paper, we examine the process margin quantified by not only by exposure latitude and depth of focus, but also the comprehensive defect –free process window. In our previous study, the behavior of missing-hole type defects was examined and robust defect suppression result was introduced by utilizing a newly developed etching recipe.1,2 In this study, we optimized CD variation and defect reduction comprehensively, to introduce successful improvement results of a wide defect process window with a narrow CD distribution.
Although EUV process was actually inserted to HVM as realistic photographic scaling driver relieving from Multiple patterning, process/material induced defect, especially missing type defect on via hole, must be serious problem and it is really considerable subject. In our previous work, the existing of latent defect around hole bottom was examined and effective solution for defect suppression utilizing robust etching technique was introduced . Additional de-scumming process before etching of under SoG layer has wider capability to suppress the missing hole defect, however, photolithographic relevant problem has to be solved in photolithography area. In this study, assuming that the origin of not-opened hole might be insolubilized potion in photo-resist film, we examined mainly interfacial reaction between photo-resist and under-layer. Historically, adhesive work(W) have been studied to prevent the peeling or collapsing of resist pattern mainly . In order to understand the reason to be insoluble the solubilized region despite exposed, de-protected and polarity changed. This paper would introduce our examination results about the infliction of resist adhesive work with modified underlayer surface and mention about our explorations of insolubilized mechanism.
CD-based process windows have been an analysis workhorse for estimating and comparing the robustness of semiconductor microlithography processes for more than 30 years. While tolerances for variation of CD are decreasing in step with the target CD size, the acceptable number of printed defects has remained flat (Hint: Zero) as the number of features increases quadratically. This disconnect between two key process estimators, CD variability and defect rate, must be addressed. At nodes that require EUV lithography, estimating the printed defects based solely on a Mean CD (“Critical Dimension”) process window is no longer predictive. The variability / distribution of the printed CDs must be engineered so that there are no failures amongst the billions of instances, rendering the Mean CD, often measured on just hundreds or thousands of instances, a poor predictor for outliers. A “defect-aware” process window, where the count of printed defects is considered in combination with more advanced statistical analysis of measured CD distributions can provide the needed predictability to determine whether a process is capable of sufficient robustness. Determining process robustness where stochastics and defects are taken into account can be simplified by determining the CD process margin. In this work we study dense contact hole arrays exposed with 0.33NA single exposure EUV lithography after both the lithography and etch steps. We describe a methodology for expanding the analysis of process windows to include more than the mean and 3σ of the data. We consider the skew and kurtosis of the distribution of measured CD results per focus-exposure condition and compare / correlate the measured CD process window results to the CD process margin.
The aim of this study is to lessen the number of defects by the simultaneous analyses of detection result via the lithography process and etch transfer performance. While defect requirements aren’t as stringent for memory devices, logic devices must be defect-free. Currently, a defect which comes from the process or material can only be detected by top-down inspection approach, however, it is difficult to detect a defect such as underlying hole. To develop 5-nm logic node, a hole pattern 15 nm or smaller is required. Identification of failure at the bottom of the hole becomes more challenging. Nevertheless, the process window margin by the amount of dose/focus is not fully explored to find the defect occurrence tendency. So far, there are reported analyses on the scaling of pattern and pitches. In this paper, we report the process margin spotted on the amount of dose and the focus depth and the comprehensive process window including a view of defect-free.
Towards realistic adoption of EUV technology, material/process induced defect must be considerable problem. Several excellent study have been introduced before and it mainly focused on the relation between defect number and pattern size and pattern pitch. Unfortunately, the study related defect transfer behavior haven’t been quite few, despite defect inspection is executed through top-down SEM.
In this study, latent defect on via hole pattern, especially, the behavior of invisible hole bottom area was focused on and we tied to clarify the exist of hidden missing defect utilizing unique RIE technique in hole image transfer onto under layer.
Lithographic scaling continues to advance by extending the life of 193nm immersion technology, and spacer-type multi-patterning is undeniably the driving force behind this trend. Multi-patterning techniques such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) have come to be used in memory devices, and they have also been adopted in logic devices to create constituent patterns in the formation of 1D layout designs. Multi-patterning has consequently become an indispensible technology in the fabrication of all advanced devices. In general, items that must be managed when using multi-patterning include critical dimension uniformity (CDU), line edge roughness (LER), and line width roughness (LWR). Recently, moreover, there has been increasing focus on judging and managing pattern resolution performance from a more detailed perspective and on making a right/wrong judgment from the perspective of edge placement error (EPE). To begin with, pattern resolution performance in spacer-type multi-patterning is affected by the process accuracy of the core (mandrel) pattern. Improving the controllability of CD and LER of the mandrel is most important, and to reduce LER, an appropriate smoothing technique should be carefully selected. In addition, the atomic layer deposition (ALD) technique is generally used to meet the need for high accuracy in forming the spacer film. Advances in scaling are accompanied by stricter requirements in the controllability of fine processing. In this paper, we first describe our efforts in improving controllability by selecting the most appropriate materials for the mandrel pattern and spacer film. Then, based on the materials selected, we present experimental results on a technique for improving etching selectivity.
Multi-patterning has been adopted widely in high volume manufacturing as 193 immersion extension, and it becomes realistic solution of nano-order scaling. In fact, it must be key technology on single directional (1D) layout design  for logic devise and it becomes a major option for further scaling technique in SAQP. The requirement for patterning fidelity control is getting savior more and more, stochastic fluctuation as well as LER (Line edge roughness) has to be micro-scopic observation aria.
In our previous work, such atomic order controllability was viable in complemented technique with etching and deposition . Overlay issue form major potion in yield management, therefore, entire solution is needed keenly including alignment accuracy on scanner and detectability on overlay measurement instruments. As EPE (Edge placement error) was defined as the gap between design pattern and contouring of actual pattern edge, pattern registration in single process level must be considerable. The complementary patterning to fabricate 1D layout actually mitigates any process restrictions, however, multiple process step, symbolized as LELE with 193-i, is burden to yield management and affordability. Recent progress of EUV technology is remarkable, and it is major potential solution for such complicated technical issues. EUV has robust resolution limit and it must be definitely strong scaling driver for process simplification. On the other hand, its stochastic variation such like shot noise due to light source power must be resolved with any additional complemented technique.
In this work, we examined the nano-order CD and profile control on EUV resist pattern and would introduce excellent accomplishments.
Gridded design rules is major process in configuring logic circuit used 193-immersion lithography. In the scaling of grid patterning, we can make 10nm order line and space pattern by using multiple patterning techniques such as self-aligned multiple patterning (SAMP) and litho-etch- litho-etch (LELE) . On the other hand, Line cut process has some error parameters such as pattern defect, placement error, roughness and X-Y CD bias with the decreasing scale. We tried to cure hole pattern roughness to use additional process such as Line smoothing . Each smoothing process showed different effect. As the result, CDx shrink amount is smaller than CDy without one additional process. In this paper, we will report the pattern controllability comparison of EUV and 193-immersion. And we will discuss optimum method about CD bias on hole pattern.
One of the practical candidates to produce 7nm node logic devices is to use the multiple patterning with 193-immersion exposure. For the multiple patterning, it is important to evaluate the relation between the number of mask layer and the minimum pitch systematically to judge the device manufacturability. Although the number of the time of patterning, namely LE(Litho-Etch) ^ x-time, and overlay steps have to be reduced, there are some challenges in miniaturization of hole size below 20nm. Various process fluctuations on contact hole have a direct impact on device performance. According to the technical trend, 12nm diameter hole on 30nm-pitch hole will be needed on 7nm node. Extreme ultraviolet lithography (EUV) and Directed self-assembly (DSA) are attracting considerable attention to obtain small feature size pattern, however, 193-immersion still has the potential to extend optical lithography cost-effectively for sub-7nm node. The objective of this work is to study the process variation challenges and resolution in post-processing for the CD-bias control to meet sub-20nm diameter contact hole. Another pattern modulation is also demonstrated during post-processing step for hole shrink. With the realization that pattern fidelity and pattern placement management will limit scaling long before devices and interconnects fail to perform intrinsically, the talk will also outline how circle edge roughness (CER) and Local-CD uniformity can correct efficiency. On the other hand, 1D Gridded-Design-Rules layout (1D layout) has simple rectangular shapes. Also, we have demonstrated CD-bias modification on short trench pattern to cut grating line for its fabrication.
The continuously scaling of complex device geometries is driving by the self-aligned multiple patterning techniques. Depending on such simplified LS scaling, FinFET design rule has been accelerated to unidirectional design layout.  In particular Fin, Gate and Metal layers are based on grating with cutting/blocking scheme, these process have become high volume manufacturing techniques in N14 and beyond.[2,3] On the other hand, immersions based pitch scaling of contact hole, via and cutmask processes are required multiple lithography and etching passes. Overlay management is not only the overlay accuracy of layer to layer, to determine the placement error and patterning fidelity in single layer. In this work, focusing on the placement in hole pattern, total placement error budget will be discussed from the viewpoints of metrology, inspection, Mask, OPC and wafer processing. In addition, hole shrink and hole healing techniques have more significant factors in terms of design-process technology co-optimization for N7 and beyond.
Proc. SPIE. 9779, Advances in Patterning Materials and Processes XXXIII
KEYWORDS: Optical lithography, Logic, Lithography, Etching, Process control, System on a chip, Photoresist materials, Line edge roughness, Photoresist processing, Critical dimension metrology, Atomic layer deposition
Gridded design rules is major process in configuring logic circuit used 193-immersion lithography. In the scaling of grid patterning, we can make 10nm order line and space pattern by using multiple patterning techniques such as self-aligned multiple patterning (SAMP) and litho-etch- litho-etch (LELE) . On the other hand, Line cut process has some error parameters such as pattern defect, placement error, roughness and X-Y CD bias with the decreasing scale. Especially roughness and X-Y CD bias are paid attention because it cause cut error and pattern defect. In this case, we applied some smoothing process to care hole roughness. Each smoothing process showed different effect on X-Y CD bias. In this paper, we will report the pattern controllability comparison of trench and block + inverse. It include X-Y CD bias, roughness and process usability. Furthermore we will discuss optimum method focused on X-Y CD bias when we use additional process such as smoothing and shrink etching .
Proc. SPIE. 9425, Advances in Patterning Materials and Processes XXXII
KEYWORDS: Line edge roughness, Optical lithography, Etching, Critical dimension metrology, Double patterning technology, Line width roughness, Photoresist materials, Lithography, Cadmium, System on a chip
Through the continuous scaling with extension of 193-immersion lithography, the multi-patterning process with the grid-based design has become nominal process for fine fabrication to relax tight pitch designs. In self-aligned type multiple patterning, 7 nm node gate pattern was reported, and it was become a focal point LER on core-pattern is essential category to control pattern placement variations. Though CD uniformity (CDU) on line pattern in self-aligned double patterning (SADP) is relatively stable caused in high thickness controllability of spacer deposition films, the variations of CDU and LER on first core pattern impinge the CDU on space and pitch pattern. In previous study, pattern fidelity of single exposure patterning was improved through photoresist smoothing process using direct-current superposition technique,.
In this paper, we will report that photoresist smoothing work in an efficient way to pattern fidelity control in self-aligned type multiple patterning.
Multi-patterning technology using 193nm immersion lithography has been used since the 22nm logic node generation and it appears that it will continue to be used as far as the 14nm generation. At the same time, the industry trend is to simplify pattern design and reduce complexity in lithography though single directional (1D) layout. On the other hand, there is increasing concern about pattern placement error in the application of this technology. This paper focuses on pattern placement variation in the process steps of pattern formation in 1D layout design, presents the results of a study on the effects of factors other than overlay accuracy on microscopic behavior, and describes techniques for improving pattern placement.
Self-aligned multiple patterning technique has enabled the further down scaling through 193 immersion lithography extension [1-5]. In particular, focus on the logic device scaling, we have finished the verification of patterning technology of up to 10nm node [6-7], we will discuss about some patterning technologies that are required to 7nm node. For critical layers in FinFET devices that presume a 1D cell design, there is also a need not just for the scaling of grating patterns but also for pattern cutting process. In 7nm node, cutting number increase in metal or fin layer, and also pattern splitting of contact or via is complicated, so both cost reduction and process controllability including EPE are strongly required. For example, inverse hardmask scheme in metal layer can improve CD variation of the Cu wiring. Furthermore hole pattern shrink technology in contact layer, by the combination with the exposure technique which has k1 0.25 or less, can achieve both cost reduction and reducing the numbers of pitch splitting. This paper presents the possibility of immersion-based multiple patterning techniques for up to 7nm node.
One of most promising technique for the extension of 193nm immersion lithography must be Self-Aligned Multiple Patterning (SAMP) at the present. We have studied this SAMP in several aspects, which are scaling capability, mitigation of process complexity, pattern fidelity, affordability and so on. On the other hand, Gridded Design Rule (GDR) concept with Single directional layout (1D layout) extended the down-scaling with 193-immersion furthermore and relieve the process variation and process complexity, represented in Optical proximity effect (OPE), by simplification of layout design. In 1D layout fabrication, Key process steps might be edge placement control on grating line and controllability of hole-shrink technique for line-cutting. This paper introduces current demonstration results on pattern transfer fidelity control and hole-shrink technique as combined with unique pattern shape repair approach.
KEYWORDS: Line edge roughness, Etching, System on a chip, Line width roughness, Lithography, Semiconductors, Critical dimension metrology, Scanning electron microscopy, Double patterning technology, Photoresist materials
Pattern roughness is expected to be an important issue in semiconductor scaling going forward. We performed
smoothing of ArF photoresists (PRs) by a PR hardening technique called direct current superposition (DCS)
cure,1) and we showed that this technique can achieve a roughness smoothing effect for PRs having various line
edge roughness (LER) conditions. Additionally, we showed that this smoothing technique has many process
advantages from the viewpoint of lithography, such as an improved mask error enhancement factor (MEEF),
expanded process window, and improved local critical dimension (CD) uniformity. We consider that these
advantages occur because of a CD healing effect caused by linear dependence of shrink amount with line width
due to the DCS cure technique.
CMOS logic at the 22nm node and below is being done with a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes have been demonstrated using a “lines and cuts” approach with good pattern fidelity and process margin, with extendibility to ~7nm. In previous studies, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective down to the 12nm node.[2,3,4,5,6] The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts. To address mask complexity and cost, OPC for the “cut” patterns was studied and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF.[3,7,8] This is significant since mask data volumes of >500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive. In our present work, we extend the scaling using SMO with “OPC Lite” beyond 12nm. The focus is on the contact pattern since a “hole” pattern is similar to a “cut” pattern so a similar technique should be useful. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops, scaled from previous studies. The contact pattern is a relatively dense layer since it connects two underlying layers – active and gate – to one overlying layer – metal-1. Several design iterations were required to get suitable layouts while maintaining circuit functionality. Experimental demonstration of the contact pattern using OPC-Lite will be presented. Wafer results have been obtained at a metal-1 half-pitch of 18nm, corresponding to the 11nm CMOS node. Additional results for other layers – FINs, local interconnect, and metal-1 – will also be discussed.
EUV lithography is one of the most promising techniques for sub-20nm half-pitch HVM devices, however it
is well known that EUVL solutions still face significant challenges. Therefore we have focused on 193
immersion extension by using a self-aligned multiple patterning (SAMP), and this technique easily enables
fine periodical patterning. Spacer patterning techniques have already been applied to sub-20nm hp advanced
devices. In general, SAMP consists of SADP, SATP, SAQP, etc. We have already introduced about
evolutional schemes and cost effective processes in past SPIE sessions.[1-12] SAQP enable further
down-scaling to 10nm hp from SADP levels, however we must consider next advanced solution for
sub-10nm hp resolution. In this paper, we will discuss about a possibility of 193 immersion extension using
SAOP (self-aligned octuple patterning).
Extreme ultraviolet (EUV) lithography is the leading candidate for sub-20nm half-pitch (hp) patterning
solution, but the development of a high-output light source is still in progress thereby delaying the adoption
of EUV for mass production. The evolution of 193nm immersion lithography-an exposure technology
currently used in the mass production of all advanced devices-must therefore be extended, and to this end,
self-aligned multiple patterning (SAMP) processes have come to be used to achieve further down scaling. To
date, we have demonstrated the effectiveness of self-aligned double patterning (SADP) and self-aligned
quadruple patterning (SAQP) as innovative processes and have reported on world-first scaling results at SPIE
on several occasions. However, for critical layers in FinFET devices that presume a 1D cell design, there is
also a need not just for the scaling of grating patterns but also for line-cutting techniques (grating and cutting).
Under the theme of existing- technology extension to sub-10nm logic nodes, this paper presents the potential
solutions of sub-10nm hp resolution by self-aligned octuple patterning (SAOP) and discusses the limits of
shrink technology in cutting patterns.
The optical projection technique with evolution of Exposure wave length (λ) and Numerical
Aperture (NA) has been historically driven Photolithographic scaling. Although the delay of
EUV tool for HVM has been concerned, scaling is going on steadily after limitation of
193nm-immersion technique. Double patterning process has been firstly adopted in 30nm node
device of memory device, and evolved step by step from SADP, SAQP to SAOP .
Self-Aligned Multiple-Patterning (SAMP) with 193-immersion is getting most promising
technology for further downwards scaling at the present. For the extension of 193-immersion, many
solutions in mask and illumination area were suggested, and these are represented by SMO (Source
and Mask Optimization) and linked to “Computational lithography”. Furthermore, the change of
device layout design to 1D (Single directional) layout  is the solution to mitigate several process
issues, which are represented by process variability, pattern fidelity and Edge placement error
This paper presents the results of observing pattern fidelity in the multiple patterning process from
many aspects and the results of testing a technique for high-accuracy management of pattern fidelity
in 1D layout.
The CMOS logic 22nm node is being done with single patterning and a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes will require the same regular layout style but with multiple patterning for critical layers. A “lines and cuts” approach is being used to achieve good pattern fidelity and process margin, with extendibility to ~7nm. In previous work, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective down to the 16nm node.[2,3,4,5] The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts. To address mask complexity and cost, OPC for the “cut” patterns was studied and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF.[6,7] This is significant since mask data volumes of <500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive. In this study, we extend the scaling using SMO with simplified OPC in a technique called “SMOLite” beyond 16nm. The same “cut” pattern is used for each set of simulations, with “x” and “y” locations for the cuts scaled for each node. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Another approach for scaling the “cut” pattern has also been studied. This involves the use of a hole pitch division process to create a grid template combined with a relatively large “selection” pattern to create cuts at the desired grid locations. Experimental demonstration of the cut approach using SMO-Lite and a grid template will be presented. Wafer results have been obtained at a line half-pitch of 20nm, which corresponds to the gate pitch at the 10nm node.
Double Patterning process is one of the most promising lithography techniques for sub-40nm half-pitch technology node. Especially, Self-aligned spacer Double Patterning (SADP) has been adopted in HVM of NAND FLASH memory device, and it is expanding to employ in DRAM and logic device. If EUVL should not be ready on time, the industry will likely further extend DP to multiple patterning. Our proposed photo-resist core SADP has wide extendibility to Self-aligned Pitch-Tripling (SATP) and Pitch-Quadrupling (SAQP) achieved 11nm hp as introduced in previous our study. Sa-MP has been required to mitigate a process complexity and cost impact. Furthermore, Process variability, Pattern fidelity, CD metrology for sub 20nm pattern also has to be considered. Beside the invention of novel technical solutions, Double-patterning process is evolving steadily and its applicability is widened.
Proc. SPIE. 8682, Advances in Resist Materials and Processing Technology XXX
KEYWORDS: Line edge roughness, Etching, Double patterning technology, Critical dimension metrology, Photoresist processing, Extreme ultraviolet, Electron beam lithography, Lithography, System on a chip, Optical lithography
The double patterning process has become a technology for extending the life of 193-nm immersion lithography. It is the most useful techniques of advancing downscaling in semiconductors and can theoretically be used scale infinitely down. For the self-aligned type of double patterning, such as self-aligned double patterning (SADP), self-aligned triple patterning (SATP), and self-aligned quadruple patterning (SAQP), we have reported that spacer-pattern processing is more difficult than line-pattern processing since the former includes more fluctuating factors, and that improving the performance of the core pattern is essential to solving this problem. Similarly, as calls for even more improvement in line edge roughness (LER) have come to be made, we have investigated the relationship between the core pattern and LER. Thus, given the importance of finding a means of securing pattern fidelity in the core pattern to improve critical dimension uniformity (CDU) and LER, we improved resist contrast resulting in dramatically reduced LER and improved spacer CD uniformity over the wafer surface. This paper presents the results of observing pattern fidelity in the double patterning process from many aspects and the results of testing a technique for high-accuracy management of pattern fidelity.
Photolithography has been a driving force behind semiconductor scaling, but the technology has been at a standstill since the development of 193-nm water-based immersion lithography. As a consequence, the double patterning process has become the standard technology for diverse types of semiconductor devices as a means of extending the life of 193-nm exposure technology. We have previously reported on the extendibility and versatility of the double patterning process, from pitch-doubling by self-aligned double patterning (SADP) to pitch-quadrupling by self-aligned quadruple patterning (SAQP). We also reported on the effectiveness of SADP technology for increasing resolution in hole patterns. While waiting for the development of extreme ultraviolet (EUV) lithography tools to be completed, it will be necessary to search out possibilities for further semiconductor scaling using the double patterning process as the mainstream technique for extending the life of 193-nm immersion lithography.
EUV lithography is one of the most promising techniques for sub 20nm half pitch HVM devices, however it is well known that EUV lithography solutions still face significant challenges. Therefore we have focused on 193 based self-aligned multiple patterning, because SAMP(SADP to SAQP) easily enables fine periodical patterning. As you know, these spacer based techniques have already been applied to NAND,DRAM,Logic mass productions. We have already introduced innovative resist core based SADP/SAQP techniques and have demonstrated results in past SPIE sessions. Although SAMP technique can be easily extend to the gridded pattern for 1D layout, the resolution limit of gridded design rule will strongly depend on hole pitch shrink technique for the cut-pattern. In this paper, we will introduce GDR demonstration result of the 10nm logic node, and discuss about the process variability relevant to them.
EUV lithography is one of the most promising techniques for the advanced patterning, however it is well known that EUVL solutions still face significant challenges. Therefore we have focused on 193 based self-aligned multiple patterning, because SAMP(SADP to SAQP) easily enables fine periodical patterning. As you know, current EUVL cannot satisfy enough resolution for sub 10nm hp critical patterning. We have already introduced innovative 193 based SADP/SAQP techniques and have demonstrated results in past SPIE sessions. we will recommend the dry cleaning technique for the pattern collapse issue of 2nd core formation. On the other hand, we have to assume the possibility of EUV+SADP in order to interpolate the EUV resolution limit. In this paper, we will discuss about the requirement process factors of 193+SAQP and EUV+SADP.
As part of the trend toward finer semiconductor design rules, the resist film thickness is getting thinner, and the etching
technology that uses resist masking is getting more difficult. To solve such a problem in recent years, the film structure
used in the resist process also is changing from the single-layer process (BARC and resist stacked film) to the multi-layer
process (Carbon hard-mask, middle layer and resist stacked film) The carbon hard-mask of multi-layer process can be
divided into two kinds, which are the CVD-carbon (CVD-C) that uses the chemical vapor deposition method and
Spin-on-carbon (SOC) that uses the spin-coating method. CVD-C is very attractive for ensuring the high etching
selection ratio, but still has major challenges in particle reduction, lower planarization of substrate and high process cost.
On the other hand, SOC is very attractive for low cost process, high level of planarization of substrate and no particles.
Against this background, we verify the development of the SOC that had the high etch selection ratio by improving
etching condition, material and SOC cure condition. Moreover, we can fabricate below 30nm SiO2 patterning and the
possibility of development with extreme ultraviolet lithography (EUVL) was suggested.
This paper reports on the results of a comprehensive process evaluation of a SOC based multi-layer technology using
lithography clusters, etching tools.
EUV lithography is one of the most promising techniques for sub-20-nm half-pitch HVM devices, however it is well
known that EUV lithography solutions still face significant challenges. Therefore we have focused on self-aligned
double patterning (SADP), because SADP easily enables fine periodical patterning. As you know, SADP techniques
have already been applied to HVM devices such as NAND Flash memory. These techniques will also be extended to
DRAM and logic mass-production devices in the near future.
In general, self-aligned multi-patterning consists of SADP, triple patterning (SATP), quadruple patterning (SAQP), etc.
We have already introduced innovative resist core based SADP/SAQP techniques and have demonstrated results in past
SPIE sessions. Our proposed SiO2 spacer is directly deposited on a resist core by a low-temperature deposition
process.SATP and SAQP enable further down-scaling to 10-15 nm hp from SADP levels, however the CD
controllability for SATP/SAQP becomes more sensitive. In this paper, we will discuss CD error budget analysis for
self-aligned multi-patterning, including a newly developed SATP scheme.
Proc. SPIE. 8325, Advances in Resist Materials and Processing Technology XXIX
KEYWORDS: Photoresist processing, Etching, Amorphous silicon, System on a chip, Line width roughness, Photoresist materials, Double patterning technology, Reactive ion etching, Optical lithography, Lithography
Self-aligned double patterning (SADP) such as multi-patterning process seems to be the most promising technology for
22nm node devices and beyond. In recent years, in order to further scaling, other multi-patterning processes such as
self-aligned triple patterning (SATP) and self-aligned quadruple patterning (SAQP) have also been studied. However,
process cost and CD controllability are major challenges since multi-patterning technology utilizes spacer processes
which-requires a larger number of etching and deposition process steps. And then we began to study the simplified
spacer process using resist core and we verified its process performance (Process window, LWR)
This paper reports on the results of a comprehensive process evaluation of multi-patterning technology using
lithography clusters, etching and deposition tools.
Self-aligned spacer Double Patterning (SADP) has been adopted in HVM of NAND FLASH memory device, because
SADP can fabricate fine periodical line pattern more easily than pitch-split type DP. Furthermore, SADP can mitigate
overlay accuracy such like pith-split type DP needed. The remarkable feature of SADP process is the adoption of a SiO2
film that can be deposited at extremely low temperatures for spacer formation. SADP and this deposition process also
produce wide applicability to density multiplication on hole pattern.
In our previous study, hole pattern fabrication below 40nmhp was examined. 30nm hp hole pattern was viable with
single 193-immersion exposure successfully with our newly developed process scheme named EKB, and ultimate
down-scaling on hole pattern, achieved to 20nm hp, was introduced utilizing cross-SADP.
In logic device manufacturing, pattern layout is getting to single directional, tabbed Gridded design rule (GDR) for the
mitigation of various lithographic issues. Although Self-aligned type DP for hole pattern can describe periodical layout,
it is really enabled for future simplified pattern layout.
In this paper, successful demonstration results would be introduced in process simplification, process extendibility, CD
controllability and further downward scaling.
Double Pattering process is one of the most promising lithography techniques for sub-40nm half-pitch technology node.
Especially, Self-aligned spacer Double Patterning (SADP) has been adopted in HVM of NAND FLASH memory device,
and it is expanding to employ in DRAM and logic device. If EUVL should not be ready on time, the industry will likely
further extend DP to multiple patterning. Our proposed photo-resist core SADP has wide extendibility to Self-aligned
Pitch-Tripling (SATP) and Pith-Quadrupling (SAQP) achieved 11nm hp as introduced in last SPIE. PR-core
technique will be most friendly for lithographer, because its property can be recognized on lithography view point.
ALD (Atomic Layer deposition) SiO2 process is the one of unique technique for multiple-patterning, and it is also
useful for pitch-doubling in hole pattern .
Beside the invention of novel technical solutions, Double-patterning process is evolving steadily and its applicability is
In this study, we would demonstrate newly developed multi-patterning techniques and optimize CD-uniformity, LWR
and process latitude.
In fine patterning process technology, the pattern shrink process technique is indispensable in addition to pitch
shrink. Tokyo Electron has previously demonstrated the application of this technique to trench-pattern shrink for
dual trench LELE, simple hole shrink for the circular pattern, and rectangle pattern shrink for cut mask of
SADP+line cut. In this paper, we introduce technology that can shrink photoresist for application to a short-trench
and contact hole pattern. Using chemical shrink as a reference for comparison, we report on the effectiveness of
TEL's original ALD SiO2 shrink process. In addition, we propose various contact pitch shrink schemes for
applying double patterning technique.
Historically, lithographic scaling has been driven by both improvements in wavelength and numerical aperture. In the
semiconductor industry, the transition to 1.35NA immersion lithography has recently been completed, and the focus is
now on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh's definition. Actually,
self-aligned spacer double patterning (SADP) has already been employed in high volume manufacturing of NAND flash
memory devices. This paper introduces demonstration results focused on the extendibility of double patterning
techniques for various device layouts.
Although numerical aperture (NA) has been significantly improved to 1.35 by the introduction of water-bases
immersion 193-nm exposure tools, the realistic minimum feature size is still limited to 40 nm even with the help of
robust resolution enhancement techniques (RETs). Double patterning processes are techniques that can be used for
fabricating etching mask patterns for 32-nm nodes and possibly for 22-nm nodes as well. Although several double
patterning processes have been introduced such as LELE, LLE and the self-aligned spacer process, LELE and
LLE suffer from the need for high overlay accuracy. The self-aligned spacer process, meanwhile, has drawn much
attention as an effective means of forming repetitive patterns easily. This paper presents results of innovative
experiments on the fabrication of 22-nm node patterns by the DP spacer process.
The reduction of line width roughness (LWR) is a critical issue in developing resist materials for EUV lithography and
LWR represents a trade-off between sensitivity and resolution. Additional post pattern processing is expected as an LWR
reduction technique without impact to resolution or sensitivity. This paper reports the LWR reducing effect of a post-development
resist-smoothing process. Approximately 20% improvement in LWR for ArF immersion exposed resist patterns was achieved for two types of resist and two illumination conditions. The LWR after BARC etching in which
resist-smoothing was applied was decreased relative to the case in which smoothing was not applied. Resist-smoothing
process also reduced LWR of an EUV exposure resist pattern by approximately 10%. These results confirm that resistsmoothing
process is robust for different resists and illumination conditions.
Numerical aperture (NA) has been significantly improved to 1.35 by the introduction of water-based immersion
193-nm exposure tools, but the realistic minimum feature size is still limited to 40 nm even with the help of robust
resolution enhancement techniques (RETs). Double patterning processes are techniques that can be used for
fabricating etching mask patterns for 32-nm nodes and possibly for 22-nm nodes as well, but the aspect ratio of
such etching mask patterns have been reduced with scaling. At the same time, dramatic improvements in the
etching durability of photo resist have not been made. This paper introduces a robust pattern-slimming process that
maintains pattern height.
Double patterning processes are techniques that can be used to form etching mask patterns for 32nm node and possibly
for 22nm node as well. The self-aligned spacer process has drawn much attention as an effective means of enabling the
formation of repetitive patterns. The self-aligned spacer process is now being used in actual device manufacturing, but it
has many process steps driving up process cost while also assuming a 1D pattern. This paper demonstrates extensions of the self-aligned spacer process by an enhanced 2D positive spacer process and a newly developed spacer DP process using a 1D negative spacer.
In the field of photolithography, a variety of resolution enhancement techniques (RETs) are being applied under the mainstream technology of 193-mm water-based immersion lithography. The resolution performance of photoresist, however, is limited at 40 nm. Double patterning (DP) is considered to be an effective technology for overcoming this limiting resolution. Many double-patterning techniques have come to be researched such as litho-etch-litho-etch (LELE), litho-litho-etch (LLE), and self-aligned spacer DP, but as the pattern-splitting type of double patterning requires high overlay accuracy in exposure equipment, the self-aligned type of double patterning has become the main approach. This paper introduces the research results of various double-patterning techniques toward 22nm nodes and touches upon newly developed elemental technologies for double patterning.
It is supposed that double patterning process is one of the promising candidates for making mask pattern for dry etching
at 32nm and 22nm node. Currently, drastic improvement of overlay of scanner is considered to be the most important
challenge and much attention has been paid to sidewall spacer process since it can avoid that problem and also can
provide easier method to fabricate patterns repeatedly. In this paper, material option of core pattern, spacer pattern and
hard mask, which are main components of this process, is presented and 32nm gate pattern is actually fabricated after
process optimization. In addition, line-width-roughness (LWR), whose reduction is becoming more and more necessary,
is measured in each process step of spacer process.