Proc. SPIE. 6152, Metrology, Inspection, and Process Control for Microlithography XX
KEYWORDS: Metrology, Materials processing, Interference (communication), Scanning electron microscopy, Line width roughness, Transistors, Field effect transistors, Critical dimension scanning electron microscopy, Line edge roughness, Tolerancing
Metrological definition and the target value of linewidth roughness (LWR) in gate pattern of MOSFETS are discussed. The effects of sampling interval of gate-LWR measurements using critical dimension scanning electron microscopy (CD-SEM) on the measurement accuracy was examined by both experiment and simulation. It was found that a 10-nm interval is sufficiently small to fully characterize roughness in a typically chosen 2-μm-long line with considering the LWR measurement error. Random image noise and intrinsic LWR variations are found to cause larger impacts on the measured value than the finiteness of the sampling interval. A practical procedure for improving the measurement accuracy is also discussed. Moreover, a methodology for establishing the gate-LWR target is proposed. Threshold-voltage shift caused by gate-LWR is given by using the LWR spectrum and the I-V curves of a transistor without LWR (ideal I-V curves). In order to calculate the target value, the ideal I-V curves, the typical gate width of the transistor and the tolerance for LWR-caused threshold-voltage variation are to be clarified.
We propose a technique using high-energy scanning electron microscope (SEM), which has the advantage of measuring 3-D structures and underlayer structures when compared to conventional low-energy SEM, to meet future metrology requirements. At first, we demonstrate that a technique using high-energy SEM has the advantages of measuring gate structures with a spatial resolution of a few nanometers. For example, a notched gate structure was most clearly visible when the beam energy is at 200 keV. Another example of a polyside gate with a sidewall spacer was most clearly visible at 100 keV. In addition, we studied the relationship between the thickness of the upper layer and beam energy at which the structure of the underlayers can be observed. The beam energy should be high enough to pass through the upper layer without the incident beam becoming broader, but low enough for the incident electrons to be backscattered at the structures in the underlayer. We could observe the line structures at a depth of 800 nm or less using an incident beam with energy from 50 to 100 keV.
Manufacturing integrated devices with faster clock speeds requires the fine control of three-dimensional gate structures, including line-edge roughness, sidewall angles, and sidewall structures, as well as the control of line widths. In addition, a way to observe underlying structures in devices with multi-layer interconnects is required. As a way to meet future metrology requirements, we propose the use of high-energy scanning electron micrscopy (SEM), which is better suited to the measurement of 3-D structures and underlying structures than conventional low-energy SEM.
High-energy SEM is shown to reveal subsurface structures that are not detected by low-energy SEM. Firstly, a motched gate structure and a polycide gate with a sidewall spacer are observed with spatial resolutions of a few nanometers. The relationship between the thickness of the upper layer and beam energy at which underlying structures are observable is also investigated. The beam should be energetic enough to pass through the upper layer without being broadened, but weak enough that incident electrons are back-scattered by the underlying structures. We were able to observe line structures at depths of up to 800 nm by using incident beams with energy levels from 50 to 100 keV.
An electron beam inspection is strongly required for HARI to detect contact and via defects that an optical inspection cannot detect. Conventionally, an e-beam inspection system is used as an analytical tool for checking the process margin. Due to its low throughput speed, it has not been used for in-line QC. Therefore, we optimized the inspection area and developed a new auto defect classification (ADC) to use with e-beam inspection as an in-line inspection tool. A
10% interval scan sampling proved able to estimate defect densities. Inspection could be completed within 1 hour. We specifically adapted the developed ADC for use with e-beam inspection because the voltage contrast images were not sufficiently clear so that classifications could not be made with conventional ADC based on defect geometry. The new ADC used the off-pattern area of the defect to discriminate particles from other voltage contrast defects with an accuracy of greater than 90%. Using sampling optimization and the new ADC, we achieved inspection and auto defect review with throughput of less than 1 and one-half hours. We implemented the system as a procedure for product defect QC and proved its effectiveness for in-line e-beam inspection.
A high-throughput high-sensitivity defect-detection technique has been developed for manufacturing 0.15-0.25- micrometers LSI devices. It incorporates a high-resolution detection systems using multi-channel detectors and a high- resolution imaging system using spatial filtering and collimated focused-beam illumination. A new algorithm called correlated local area statistical threshold enables this technique to achieve a sensitivity of 0.15 micrometers on front- end processes and 0.3 micrometers on back-end processes and a high throughput.
The effective combination of the conventional in-line wafer inspection technique and yield prediction technique has become an important issue in order to reduce time for the development of LSI and to ramp the yield. At the last SPIE, we presented the change in the defect modes from conventional planarization process to CMP process and proposed the new inspection system for the CMP process. That is, the dark field type with the bright field optics which has the function to measure defect sizes. We now prose a new function to recognize automatically whether defects are either on or off the patterns. By monitoring the intensities of scattered light for the adjacent die at the positions where the defects are detected, the system can recognize that defects are either on or off the patterns. Using this new function, the patterned wafer inspection system can offer information about both the defect size and its fatality. As a result, we can evaluate the yield prediction and analyze the variation in the predicted yield quickly.
In this paper, it is described that (1) Various type of SOI wafers have each optimum laser illumination mode, (2) Using this optimum laser illumination, 0.1 - 0.3 micrometer particle detection sensitivity has been achieved. (3) By measuring the noise element of scattered light from SOI surface, failure mode can be determined. The performance of the particle detection for each type of wafer and the result of surface roughness failure is also discussed.
With the application of chemical mechanical polishing (CMP), particles become the main defect mode among the various modes of defects. Therefore, particle control becomes increasingly important. For the effective particle control, we need to control not only the number of defects but also the size of defects. However, a conventional particle inspection system using laser scattering could not obtain the information of the accurate particle size. We have developed the new system which can obtain the information of accurate particle size by using image processing. The particle size measured by the new system well agrees with the size measured by SEM. With the new system, we can operate the killer particle control effectively.
An effective and practical control technology of critical dimensions for submicron VSLI is presented. An ARCOR (Anti-Reflective Coating On Resist) process was improved, which is applied as a transparent type anti-reflective coating. A water soluble and low refractive index film was developed for this purpose. The following five items were measured experimentally and discussed : (1) amplitude of swing curve's dependence on resist thickness, (2) thickness latitude of the ARCOR film, (3) photo speed, (4) CD variations in a submicron DRAM and (5) alignment accuracy with a bright field alignment system.
New indexes to evaluate and simulate the resolution power of the UV resists based on the dissolution rate curve as it relates to local inhibitor concentration are proposed. Optical parameters and the dissolution rate curve of commercially available resists were measured and studied to show their effect on the resolution power. The optical parameters A B and C had very little effect on the resolution power while the dissolution rate curve greatly effected the resolution power. Two indexes are extracted from the dissolution rate curve. One is the contrast of the dissolution rate and the other is the range of the dissolution rate. By using these indexes the resolution power can be easily described. The indexes of an imaginary resist required for a 0. 5. tm process is shown. 1 .