We compare the noise performance of two optimized readout chains that are based on 4T pixels and featuring the same bandwidth of 265kHz (enough to read 1Megapixel with 50frame/s). Both chains contain a 4T pixel, a column amplifier and a single slope analog-to-digital converter operating a CDS. In one case, the pixel operates in source follower configuration, and in common source configuration in the other case. Based on analytical noise calculation of both readout chains, an optimization methodology is presented. Analytical results are confirmed by transient simulations using 130nm process. A total input referred noise bellow 0.4 electrons RMS is reached for a simulated conversion gain of 160μV/e−. Both optimized readout chains show the same input referred 1/f noise. The common source based readout chain shows better performance for thermal noise and requires smaller silicon area. We discuss the possible drawbacks of the common source configuration and provide the reader with a comparative table between the two readout chains. The table contains several variants (column amplifier gain, in-pixel transistor sizes and type).
Proc. SPIE. 7875, Sensors, Cameras, and Systems for Industrial, Scientific, and Consumer Applications XII
KEYWORDS: Data compression, Image compression, 3D acquisition, High dynamic range image sensors, Image quality, Image sensors, High dynamic range imaging, Transistors, Integrated circuits, 3D image processing
High Dynamic Range (HDR) Image sensors aim at having a dynamic over 120dB. Compared to classical architectures
this is obtained at the cost of a higher transistor count, thus lower fill factor. Three Dimensional integrated circuits (3DIC)
somehow change the constraints, photodiodes and electronics can be stacked on different layers, giving more
processing powers without compromising the fill factor.
In this paper, we propose an original architecture for a high dynamic 3D image sensor with data reduction obtained by
local compression. HDR acquisition is based on a floating point coding shared by a group of pixel (macro-pixel), thus
giving also a first level of compression. A second level of compression is performed by using a Discrete Cosine
Transform (DCT). With this new concept a good image quality (PSNR of about 40 dB) and a high dynamic range (120
dB) are obtained within a pixel area of 5μm×5μm.
Proc. SPIE. 7834, Electro-Optical and Infrared Systems: Technology and Applications VII
KEYWORDS: Staring arrays, Readout integrated circuits, Long wavelength infrared, Signal to noise ratio, Mercury cadmium telluride, Sensors, Electrons, Photodiodes, High dynamic range imaging, Prototyping
CEA-Leti MINATEC has been involved in infrared focal plane array (IRFPA) development since many years, with performing HgCdTe in-house process from SWIR to LWIR and more recently in focusing its work on new ROIC architectures. The trend is to integrate advanced functions into the CMOS design for the purpose of applications
demanding a breakthrough in Noise Equivalent Temperature Difference (NETD) performances (reaching the mK in LWIR band) or a high dynamic range (HDR) with high-gain APDs. In this paper, we present a mid-TV format focal plane array (FPA) operating in LWIR with 25μm pixel pitch, including a new readout IC (ROIC) architecture based on
pixel-level charge packets counting. The ROIC has been designed in a standard 0.18μm 6-metal CMOS process, LWIR n/p HgCdTe detectors were fabricated with CEA-Leti in-house process. The FPA operates at 50Hz frame rate in a snapshot integrate-while-read (IWR) mode, allowing a large integration time. While classical pixel architectures are limited by the charge well capacity, this architecture exhibits a large well capacity (near 3Ge-) and the 15-bit pixel level ADC preserves an excellent signal-to-noise ratio (SNR) at full well. These characteristics are essential for LWIR FPAs
as broad intra-scene dynamic range imaging requires high sensitivity. The main design challenges for this digital pixel
array (SNR, power consumption and layout density) are discussed. The electro-optical results demonstrating a peak NETD value of 2mK and images taken with the FPA are presented. They validate both the pixel-level ADC concept and its circuit implementation. A previously unreleased SNR of 90dB is achieved.
CEA Leti has recently developed a new readout IC (ROIC) with pixel-level ADC for cooled infrared focal plane arrays
(FPAs). It operates at 50Hz frame rate in a snapshot Integrate-While-Read (IWR) mode. It targets applications that
provide a large amount of integrated charge thanks to a long integration time. The pixel-level analog-to-digital
conversion is based on charge packets counting. This technique offers a large well capacity that paves the way for a
breakthrough in NETD performances. The 15 bits ADC resolution preserves the excellent detector SNR at full well
(3Ge-). These characteristics are essential for LWIR FPAs as broad intra-scene dynamic range imaging requires high
sensitivity. The ROIC, featuring a 320x256 array with 25μm pixel pitch, has been designed in a standard 0.18μm CMOS
technology. The main design challenges for this digital pixel array (SNR, power consumption and layout density) are
discussed. The IC has been hybridized to a LWIR detector fabricated using our in-house HgCdTe process. The first
electro-optical test results of the detector dewar assembly are presented. They validate both the pixel-level ADC concept
and its circuit implementation. Finally, the benefit of this LWIR FPA in terms of NETD performance is demonstrated.
LETI has been involved in IRFPA development since 1978; the design department (LETI/DCIS) has focused its
work on new ROIC architecture since many years. The trend is to integrate advanced functions into the
CMOS design to achieve cost efficient sensors production. Thermal imaging market is today more and more
demanding of systems with instant ON capability and low power consumption.
The purpose of this paper is to present the latest developments of fixed pattern noise continuous time correction.
Several architectures are proposed, some are based on hardwired digital processing and some are purely analog.
Both are using scene based algorithms. Moreover a new method is proposed for simultaneous correction of pixel
offsets and sensitivities. In this scope, a new architecture of readout integrated circuit has been implemented; this
architecture is developed with 0.18μm CMOS technology. The specification and the application of the ROIC are
discussed in details.
This paper firstly presents an asynchronous analog to digital technique that is well suited for an in-pixel implementation
in an X-ray or Infra-Red image sensor. The principle which consists in counting charge packets coming from the detector
is also called "charge-balancing technique". Simulation and experimental results on a 0.13μm process test-chip are given
and a 16 bit dynamic range is reached. Secondly a new enhancement method is described. This method controls the LSB
of the A/D conversion as the input current (from the detector) varies, so that a floating point coding is carried out. The
consequences are a wider dynamic range (19 bits at least) as well as a reduction of the technological fluctuations
between two different pixels. On this work in progress, implementation in a 150x150μm<sup>2</sup> pixel is briefly commented.