For 2x nm node semiconductor devices and beyond, more aggressive resolution enhancement techniques (RETs) such as source-mask co-optimization (SMO), litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) are utilized for the low k1 factor lithography processes. In the SADP process, the pattern fidelity is extremely critical since a slight photoresist (PR) top-loss or profile roughness may impact the later core trim process, due to its sensitivity to environment. During the subsequent sidewall formation and core removal processes, the core trim profile weakness may worsen and induces serious defects that affect the final electrical performance. To predict PR top-loss, a rigorous lithography simulation can provide a reference to modify mask layouts; but it takes a much longer run time and is not capable of full-field mask data preparation. In this paper, we first brought out an algorithm which utilizes multi-intensity levels from conventional aerial image simulation to assess the physical profile through lithography to core trim etching steps. Subsequently, a novel correction method was utilized to improve the post-etch pattern fidelity without the litho. process window suffering. The results not only matched PR top-loss in rigorous lithography simulation, but also agreed with post-etch wafer data. Furthermore, this methodology can also be incorporated with OPC and post-OPC verification to improve core trim profile and final pattern fidelity at an early stage.
As the cost of manufacturing high-end semiconductors continues to increase, the value of combining and streamlining
metrology steps also increases. The two critical metrology steps for litho control are 1) overlay and 2) CD. In this study,
the authors demonstrate the capability of just such a combination CD and Overlay metrology solution to improve not
only the cost of manufacturing but also the quality of data and information feedback for better scanner control in high
The authors demonstrate how using imaging and scatterometry technology on a single platform can provide a
comprehensive litho control solution for both CD and overlay in the litho module. In the study, the authors will use full
stack wafers from an advanced process node running in high volume manufacturing. Specifically, data will be generated
using PROLITH for lithographic simulations for optimal target designs and then empirical data will be collected using
the Archer 300 LCM from which optimal target selection and system performance will be determined and validated on
wafers using this advanced process technology.
As IC dimensions continue to shrink beyond the 22nm node, optical single exposure cannot sustain the resolution
required and various double patterning techniques have become the main stream prior to the availability of EUV
lithography. Among various kinds of double patterning techniques, positive splitting pitch lithography-etch-lithographyetch
(LELE) double patterning is chosen for printing complex foundry circuit designs. Tighter circuit CD and process
margin control in such positive splitting pitch LELE double patterning process becomes increasingly critical especially
for topography issues induced by the 1st mask patterning with the 2nd mask exposure. In this paper, laser parameters,
topography issues with the 2nd mask exposure, and SMO effects on CD performances are described in terms of the
proximity CD portion of the scanner CD budget. Laser parameters, e.g. spectral shape and bandwidth, were input into the
photolithography simulator, Prolith, to calculate their impacts on circuit CD variation. Mask-bias dependent lithographic
performance was calculated and used to illustrate the importance of well-controlled laser performance parameters.
Recommended laser bandwidth, mask bias and topography requirements are proposed, based on simulation results to
ensure that the tight CD control (< 1nm) required for advanced technology node products can be achieved.
Tight circuit CD control in a photolithographic process has become increasingly critical particularly for advanced
process nodes below 32nm, not only because of its impact on device performance but also because the CD control
requirements are approaching the limits of measurement capability. Process stability relies on tight control of every
factor which may impact the photolithographic performance. The variation of circuit CD depends on many factors, for
example, CD uniformity on reticles, focus and dose errors, lens aberrations, partial coherence variation, photoresist
performance and changes in laser spectrum. Laser bandwidth and illumination partial coherence are two significant
contributors to the proximity CD portion of the scanner CD budget. It has been reported that bandwidth can contribute
to as much as 9% of the available CD budget, which is equivalent to ~0.5nm at the 32nm node. In this paper, we are
going to focus on the contributions of key laser parameters e.g. spectral shape and bandwidth, on circuit CD variation for
an advanced node logic device. These key laser parameters will be input into the photolithography simulator, Prolith, to
calculate their impacts on circuit CD variation. Stable though-pitch proximity behavior is one of the critical topics for
foundry products, and will also be described in the paper.
Beyond 40nm lithography node, mask topograpy is important in litho process. The rigorous EMF simulation should
be applied but cost huge time. In this work, we compared experiment data with aerial images of thin and thick mask
models to find patterns which are sensitive to mask topological effects and need rigorous EMF simulations. Furthur more,
full physical and simplified lumped (LPM) resist models were calibrated for both 2D and 3D mask models. The accuracy
of CD prediction and run-time are listed to gauge the most efficient simulation. Although a full physical resist model
mimics the behavior of a resist material with rigor, the required iterative calculations can result in an excessive execution
time penalty, even when simulating a simple pattern. Simplified resist models provide a compromise between
computational speed and accuracy.
The most efficient simulation approach (i.e. accurate prediction of wafer results with minimum execution time) will
have an important position in mask 3D simulation.