In this paper, we discuss a hardware based low complexity JPEG 2000 video coding system. The
hardware system is based on a software simulation system, where temporal redundancy is exploited by coding of differential frames which are arranged in an adaptive GOP structure whereby the GOP
structure itself is determined by statistical analysis of differential frames. We present a hardware video
coding architecture which applies this inter-frame coding system to a Digital Signal Processor (DSP). The system consists mainly of a microprocessor (ADSP-BF533 Blackfin Processor) and a JPEG 2000 chip (ADV202).