Dr. Artur P. Balasinski Profile

Dr. Artur P. Balasinski

Sr Principal Engineer at Cypress Semiconductor Corp

SPIE Involvement:

Scholarship Committee | Conference Program Committee | Author

Publications (30)

PROCEEDINGS ARTICLE | October 1, 2013

Looking for simple engineering solutions in DFM patents

Proc. SPIE. 8886, 29th European Mask and Lithography Conference

KEYWORDS: Lithography, Optical lithography, Patents, Data modeling, Calibration, Etching, Manufacturing, Design for manufacturing, Optical proximity correction, Semiconducting wafers

Read Abstract

PROCEEDINGS ARTICLE | September 27, 2011

Mask cycle time reduction for foundry projects

Proc. SPIE. 8166, Photomask Technology 2011

KEYWORDS: Semiconductors, Data modeling, Data storage, Databases, Manufacturing, Photomasks, Computer aided design, Document management, Data communications, Design for manufacturability

Read Abstract

PROCEEDINGS ARTICLE | December 28, 2007

SoC variability evaluation and reduction

Proc. SPIE. 6798, Microelectronics: Design, Technology, and Packaging III

KEYWORDS: Lithography, Calibration, Etching, Manufacturing, Design for manufacturing, Field effect transistors, Optical proximity correction, Computer aided design, Analog electronics, System on a chip

Read Abstract

PROCEEDINGS ARTICLE | December 28, 2007

New type of dummy layout pattern to control ILD etch rate

Proc. SPIE. 6798, Microelectronics: Design, Technology, and Packaging III

KEYWORDS: Oxides, Etching, Dielectrics, Silicon, Chemistry, Design for manufacturing, Field effect transistors, Optical proximity correction, Deposition processes, Semiconducting wafers

Read Abstract

PROCEEDINGS ARTICLE | December 21, 2007

Patterning techniques for next generation IC's

Proc. SPIE. 6798, Microelectronics: Design, Technology, and Packaging III

KEYWORDS: Lithography, Metrology, Optical lithography, Etching, Design for manufacturing, Photomasks, Extreme ultraviolet, Double patterning technology, Nanoimprint lithography, Overlay metrology

Read Abstract

PROCEEDINGS ARTICLE | October 30, 2007

Mask manufacturability improvement by MRC

Proc. SPIE. 6730, Photomask Technology 2007

KEYWORDS: Metrology, Databases, Error analysis, Manufacturing, Inspection, Control systems, Photomasks, Optical proximity correction, Computer aided design, Semiconducting wafers

Read Abstract

PROCEEDINGS ARTICLE | October 30, 2007

From rule to model-based design: A need for DfP criteria?

Proc. SPIE. 6730, Photomask Technology 2007

KEYWORDS: Particles, Manufacturing, Design for manufacturing, Field effect transistors, Semiconducting wafers, Tolerancing, Yield improvement, Model-based design, Chemical mechanical planarization, Design for manufacturability

Read Abstract

SPIE Journal Paper | July 1, 2007

Layout techniques and rules to reduce process-related variability

Balasinski, Artur , Cetin, Joseph , Karklin, Linard

JM3 Vol. 6 Issue 03

KEYWORDS: Computer aided design, Optical proximity correction, Critical dimension metrology, Design for manufacturing, Field effect transistors, Manufacturing, Photomasks, Lithography, Analog electronics, Etching

Read Abstract

PROCEEDINGS ARTICLE | March 21, 2007

Intelligent fill pattern and extraction methodology for sensitive RF/analog or SoC products

Proc. SPIE. 6521, Design for Manufacturability through Design-Process Integration

KEYWORDS: Capacitors, Metals, Dielectrics, Capacitance, Field effect transistors, Resistors, Tolerancing, Capacitive coupling, System on a chip, Intelligent sensors

Read Abstract

Distribution of mask pattern density of isolating or conducting, layers of the die, such as active, poly, or metals, impacts product voltage tolerance and frequency response. At active level, nonuniform pattern density lowers punch-through or breakdown voltages. At metal levels, planarity issues give rise to high via resistances and variations of inter-layer capacitive coupling. Devices required to build an SoC product such as precision resistors, inductors, RF FETs, and capacitors, have diversified geometry characteristics. Usually, the differences in pattern density they cause over the die cannot be mitigated at design stage. Therefore, die pattern density has to be made uniform at die integration stage, by global addition of fill features (waffles). This presents significant challenge as the criteria for this addition are often contradictory or difficult to meet. The basic, but time consuming way of equalizing pattern density calls for manual adding of dummy features. In comparison, a simplistic, automated geometric approach is to add fill pattern of fixed density, which would then become target pattern density of the die. However, it may not be possible to equalize pattern density over all the regions even allowing for some changes in the die architecture in the course of either manual or automated waffling process. In addition, the approach tends to add dummy features even if unnecessary, creating local extremes of pattern density. Such outcome is not always preferred by the product RF/analog applications, which can be compromised by capacitive coupling through the waffles. In our methodology proposed in this work, the die pattern density is first analyzed, followed by the adjustable, intelligent fill of dynamic density. This way, it is possible to keep the original pattern density and work only on the areas of small density. We also propose to adjust the standard cell methodology in order to enable pre-die level modifications of pattern density and its extraction and ensure that all the required blocks could be placed on the product with their parasitics accounted for.

PROCEEDINGS ARTICLE | March 21, 2007

Cost-performance tradeoff between design and manufacturing: DfM or MfD?

Proc. SPIE. 6521, Design for Manufacturability through Design-Process Integration

KEYWORDS: Manufacturing, Reliability, Design for manufacturing, Photomasks, Optical proximity correction, Computer aided design, Semiconducting wafers, Yield improvement, Electronic design automation, Design for manufacturability

Read Abstract

Design, CAD, and manufacturing are focused on optimizing translation methodology from electrical design to physical layout, and finally to mask data. The general goal is to improve integrated circuit (IC) functionality, reliability, manufacturability, testability, etc., using Design-for-X-ability (DfX) rules. Among those, the key role is played by DfM which is most directly related to the yield and therefore, the profit. A lot of pressure is being put on design to improve their understanding of all technology implementation issues, such that the mask pattern generated out of design layout would be "correct by construction" and comply with all of them. One can expect that such DfM-compliant layout should require significant effort to create, and its salient features would include: Manhattan geometries, and restricted grid for critical geometries, such as poly gates, large enclosures of the active area in the corners of implant layers, complete symmetry and proximity of the matched devices on all masking levels, minimal amount of jogs even for the complex features, neat alignment of source and drain contacts, line ends of gates and interconnects, doubled contacts and vias, etc. The question is if the cost of following all these practices at design time is not higher than that of other design improvement options. One alternative approach is to automatically adjust the "draft" layout using CAD post-processing such that all geometries would be optimized to conform to the DfM rules. Another approach to the DfM methodology is to improve the manufacturing capabilities such that the process tools would be able to achieve high yield for a layout which conforms only to some basic set of rules. This approach becomes even more relevant when the product line tries to address only selected DfM issues to improve die performance where it is most needed. We discussed the layout flow charts to determine the best approach, depending on the direct cost of the solution, the wafer volume, product time to market, and the risks involved.

PROCEEDINGS ARTICLE | October 20, 2006

A procedure and program to calculate shuttle mask advantage

Proc. SPIE. 6349, Photomask Technology 2006

KEYWORDS: Reticles, Visualization, Databases, Manufacturing, Photomasks, Algorithm development, Semiconducting wafers, Product engineering, Resolution enhancement technologies, Design for manufacturability

Read Abstract

A well-known recipe for reducing mask cost component in product development is to place non-redundant elements of layout databases related to multiple products on one reticle plate [1,2]. Such reticles are known as multi-product, multi-layer, or, in general, multi-IP masks. The composition of the mask set should minimize not only the layout placement cost, but also the cost of the manufacturing process, design flow setup, and product design and introduction to market. An important factor is the quality check which should be expeditious and enable thorough visual verification to avoid costly modifications once the data is transferred to the mask shop. In this work, in order to enable the layer placement and quality check procedure, we proposed an algorithm where mask layers are first lined up according to the price and field tone [3]. Then, depending on the product die size, expected fab throughput, and scribeline requirements, the subsequent product layers are placed on the masks with different grades. The actual reduction of this concept to practice allowed us to understand the tradeoffs between the automation of layer placement and setup related constraints. For example, the limited options of the numbers of layer per plate dictated by the die size and other design feedback, made us consider layer pairing based not only on the final price of the mask set, but also on the cost of mask design and fab-friendliness. We showed that it may be advantageous to introduce manual layer pairing to ensure that, e.g., all interconnect layers would be placed on the same plate, allowing for easy and simultaneous design fixes. Another enhancement was to allow some flexibility in mixing and matching of the layers such that non-critical ones requiring low mask grade would be placed in a less restrictive way, to reduce the count of orphan layers. In summary, we created a program to automatically propose and visualize shuttle mask architecture for design verification, with enhancements to due to the actual application of the code.

PROCEEDINGS ARTICLE | October 20, 2006

Mask complexity reduction, quality assurance, and yield improvement through reduced layout variability

Proc. SPIE. 6349, Photomask Technology 2006

KEYWORDS: Silicon, Manufacturing, Design for manufacturing, Photomasks, Field effect transistors, Optical proximity correction, Computer aided design, Critical dimension metrology, Standards development, Resolution enhancement technologies

Read Abstract

PROCEEDINGS ARTICLE | November 8, 2005

Inverse lithography technology: verification of SRAM cell pattern

Proc. SPIE. 5992, 25th Annual BACUS Symposium on Photomask Technology

KEYWORDS: Semiconductors, Lithography, Reticles, Calibration, Silicon, Scanning electron microscopy, Optical inspection, Photomasks, Optical proximity correction, Semiconducting wafers

Read Abstract

PROCEEDINGS ARTICLE | November 4, 2005

DfM requirements and ROI analysis for system-on-chip

Proc. SPIE. 5992, 25th Annual BACUS Symposium on Photomask Technology

KEYWORDS: Databases, Silicon, Manufacturing, Design for manufacturing, Photomasks, Optical proximity correction, Computer aided design, Failure analysis, System on a chip, Design for manufacturability

Read Abstract

PROCEEDINGS ARTICLE | June 28, 2005

Multi-layer masks: manufacturability considerations

Proc. SPIE. 5853, Photomask and Next-Generation Lithography Mask Technology XII

KEYWORDS: Reticles, Optical lithography, Manufacturing, Resistance, Control systems, Photomasks, Optical alignment, Semiconducting wafers, Overlay metrology, Standards development

Read Abstract

PROCEEDINGS ARTICLE | May 10, 2005

Impact of overlay metrology on design rule tolerance and shrinkability

Proc. SPIE. 5752, Metrology, Inspection, and Process Control for Microlithography XIX

KEYWORDS: Reticles, Databases, Metals, Silicon, Photomasks, Optical alignment, Critical dimension metrology, Semiconducting wafers, Tolerancing, Overlay metrology

Read Abstract

Design rule development for next technology generations depends on the progress in the optical and mechanical properties of steppers and photomasks. For two basic types of design rules: those that define minimum critical dimensions (CD, line and space), and those that define overlay/enclosure (OL) between layers, the shrinkpaths with technology nodes are generally unrelated. The min CD rules are dictated by stepper resolution limits and mask minimum features, the overlay rules - by the respective mechanical tolerances of the printing hardware. However, successful shrinks of design databases to the subsequent technology nodes require that all the design rules be scaled, preferably by the same factor. In this work, we first discuss the impact of the different types of rules on the layout architecture. We then show how one derives OL design rules from alignment tolerances. One method is based on the Lynch numbers (LN), corresponding to the misalignment budget ensuring that the OL yield loss is no more than 0.5% per mask level. However, LN’s are not directly measured in the fab. An alternative method is based on the 3s misregistration error. We demonstrate that these two methods show similar results for several types of masks and steppers. Finally, we show how the trend of overlay tolerance (OL) improvement compares with the trend of min feature size (CD) reduction. The data shows an offset between the OL and the CD trends amounting to 14 nm for the 45 nm technology node. This offset, which we call the overlay tolerance gap, means that enclosure rules would, in general, scale at a slower pace compared to the rules dictated by the linear CD shrink. One should note that the OL tolerance is influenced by matching of reticles and steppers and can be improved by the rework of wafers in line. In summary, we discuss theoretical and manufacturing-related aspects of overlay metrology, to advance design rule shrinks aligned with technology roadmap.

PROCEEDINGS ARTICLE | December 6, 2004

Multilayer and multiproduct masks: cost reduction methodology

Proc. SPIE. 5567, 24th Annual BACUS Symposium on Photomask Technology

KEYWORDS: Multilayers, Reticles, Databases, Silicon, Inspection, Printing, Photomasks, Dysprosium, Semiconducting wafers, Standards development

Read Abstract

PROCEEDINGS ARTICLE | December 6, 2004

Device analysis: a way to reduce patterning cost at mask and wafer level?

Proc. SPIE. 5567, 24th Annual BACUS Symposium on Photomask Technology

KEYWORDS: Reticles, Optical lithography, Image processing, Silicon, Photomasks, Field effect transistors, Optical proximity correction, Critical dimension metrology, Semiconducting wafers, Device simulation

Read Abstract

PROCEEDINGS ARTICLE | May 3, 2004

A 65-nm node SRAM solution using alt-PSM with ArF lithography

Proc. SPIE. 5379, Design and Process Integration for Microelectronic Manufacturing II

KEYWORDS: Lithography, Lithographic illumination, Manufacturing, Control systems, Photomasks, Critical dimension metrology, Semiconducting wafers, Optics manufacturing, Binary data, Fiber optic illuminators

Read Abstract

PROCEEDINGS ARTICLE | May 3, 2004

A methodology to analyze circuit impact of process-related MOSFET geometry

Proc. SPIE. 5379, Design and Process Integration for Microelectronic Manufacturing II

KEYWORDS: Image visualization, Silicon, Diffusion, Distortion, Photomasks, Transistors, Field effect transistors, Optical proximity correction, Critical dimension metrology, Device simulation

Read Abstract

PROCEEDINGS ARTICLE | May 3, 2004

Optimization of interconnection layout for multitransistor cell shrinkability

Proc. SPIE. 5379, Design and Process Integration for Microelectronic Manufacturing II

KEYWORDS: Oxides, Etching, Metals, Diffusion, Printing, Photomasks, Optical proximity correction, Optical alignment, Tolerancing, Phase shifts

Read Abstract

SPIE Journal Paper | April 1, 2004

Optimization of sub-100-nm designs for mask cost reduction

Balasinski, Artur

JM3 Vol. 3 Issue 02

KEYWORDS: Photomasks, Field effect transistors, Optical proximity correction, Critical dimension metrology, Monte Carlo methods, Transistors, Computer simulations, Reticles, Metals, Computer aided design

Read Abstract

PROCEEDINGS ARTICLE | December 17, 2003

Optimization of dummy pattern for mask data size reduction

Proc. SPIE. 5256, 23rd Annual BACUS Symposium on Photomask Technology

KEYWORDS: Oxides, Databases, Metals, Manufacturing, Capacitance, Photomasks, Computer aided design, Neodymium, Semiconducting wafers, Chemical mechanical planarization

Read Abstract

PROCEEDINGS ARTICLE | July 2, 2003

Mask cost for sub-100-nm technologies: stopping a runaway?

Proc. SPIE. 5043, Cost and Performance in Integrated Circuit Creation

KEYWORDS: Reticles, Databases, Manufacturing, Monte Carlo methods, Photomasks, Transistors, Field effect transistors, Optical proximity correction, Computer aided design, Critical dimension metrology

Read Abstract

PROCEEDINGS ARTICLE | May 28, 2003

Accuracy vs. complexity: tradeoffs in OPC options

Proc. SPIE. 5148, 19th European Conference on Mask Technology for Integrated Circuits and Microcomponents

KEYWORDS: Cadmium, Data modeling, Calibration, Databases, Error analysis, Silicon, Optical proximity correction, Computer aided design, Model-based design, Solid modeling

Read Abstract

PROCEEDINGS ARTICLE | August 1, 2002

Novel procedure for mask disposition using electrical signatures of mask defects

Proc. SPIE. 4754, Photomask and Next-Generation Lithography Mask Technology IX

KEYWORDS: Defect detection, Particles, Ions, Silicon, Manufacturing, Inspection, Photomasks, Transistors, Field effect transistors, Critical dimension metrology

Read Abstract

PROCEEDINGS ARTICLE | July 30, 2002

Subwavelength lithography: an impact of photo mask errors on circuit performance

Proc. SPIE. 4691, Optical Microlithography XV

KEYWORDS: Lithography, Optical lithography, Lithographic illumination, Error analysis, Manufacturing, Monte Carlo methods, Photomasks, Field effect transistors, Semiconducting wafers, Resolution enhancement technologies

Read Abstract

PROCEEDINGS ARTICLE | July 12, 2002

Impact of subwavelength CD tolerance on device performance

Proc. SPIE. 4692, Design, Process Integration, and Characterization for Microelectronics

KEYWORDS: Optical lithography, Silicon, Optical simulations, Transistors, Field effect transistors, Optical proximity correction, Critical dimension metrology, Semiconducting wafers, Tolerancing, Resolution enhancement technologies

Read Abstract

PROCEEDINGS ARTICLE | September 14, 2001

Advanced procedure to evaluate process performance at very low k1 based on device parameters linked to lithography and process data:II. Verification of cell layout based on integration of optical an

Proc. SPIE. 4346, Optical Microlithography XIV

KEYWORDS: Cadmium, Metals, Silicon, Resistance, Optical simulations, Integrated optics, Transistors, Field effect transistors, Optical proximity correction, Critical dimension metrology

Read Abstract

PROCEEDINGS ARTICLE | September 2, 1997

Monitoring process-induced oxide breakdown and its correlation to interface traps

Proc. SPIE. 3215, In-Line Characterization Techniques for Performance and Yield Enhancement in Microelectronic Manufacturing

KEYWORDS: Oxides, Capacitors, Metals, Dielectrics, Interfaces, Nondestructive evaluation, Field effect transistors, Semiconducting wafers, Testing and analysis, Plasma

Read Abstract