Historically, lithographic scaling was driven by both improvements in wavelength and numerical aperture. Recently,
the semiconductor industry completed the transition to 1.35NA immersion lithography. The industry
is now focusing on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh
diffraction. Here, the IBM Alliance demonstrates the extendibility of several double patterning solutions that
enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through
innovative processes. This paper details a set of solutions that have enabled early 22 nm learning through careful
We show that a conformal mapping of the type, W = z π/α, describes how a shape of a 45° rotated cross transforms into a contact hole. We discuss its relevance to corner rounding seen on raster beam pattern generators.
The ALTA 4300 system has been used to successfully write many advanced design layers previously only feasible with 50kV vector shaped beam tools. In order to further enlarge the application space of this high productivity an aerial image enhancement technique has been developed to deliver mask patterns that more closely match pattern data for corners and jogs. This image enhancement is done in real time in the ALTA system’s rasterizer by modifying the gray level mapping of pixels near the corner vertexes. SEM measurements of corner rounding with standard rasterization and the enhanced rasterization show an improvement of corner rounding radius from ~205 to ~132 nm. A direct comparison of SEM micrographs show no qualitative difference between vector scan mask features and those written with aerial image enhancement. This convincingly demonstrates that the ALTA 4300 system with the new image enhancement can write many layers requiring vector scan corner acuity.