Recent trends show an explosion in the amount of data being created each year. In response to this trend new system architectures optimized for data-centric workloads are being developed. These architectures can only be brought to fruition by developing new technologies to transmit, compute, and store data. My talk will focus on the impact of photonics, and silicon photonics in particular, on these trends and discuss the work being done at HPE labs to advance these technologies
Initially, we’ll discuss an SOI based, carrier injection micro-ring modulator. The static optical and electrical characteristics of this device will be reviewed and described. Thermal control and modulation mechanisms with pre-emphasis will be outlined. Automated wafer-lever optical/electrical results from volume foundries (Leti and STMicro) used for PDK/Verilog model development will be reviewed, along with experimental data on direct modulation to 25 Gb/s, crosstalk at various DWDM channel separations, and demonstrations with an external quantum-dot based comb laser with 80 and 50GHz channel spacing.
Following this, our work on directly modulated hybrid quantum-well ring lasers will be reviewed in design, fabrication. Experimental results for modulation at 12.5 Gb/s/channel, integration with MOS capacitor for wavelength control and modulation and a thermal shunt for temperature management will highlight the advantages of this technology that may be exploited. Subsequently, our work on hybrid quantum-dot based comb lasers for on-chip DWDM sources will be discussed in their details of physical operation, demonstrating successful mode-locking and noise-free operation across the 20-80C thermal range. Our work on the integration of on-chip APDs from a CMOS-compatible processes will also be reviewed, demonstrating error-free operation at 12.5 Gb/s and 25 Gb/s with a sensitivity of -26dBm and -16dBm, respectively. The use of APDs will drastically decrease the overall power consumption of the interconnect, lowering total cost of ownership. Finally, our most recent progress on integration of the silicon photonics with CMOS by a flip-chip will be reviewed showing high-speed modulation and thermal control for a multi-channel DWDM transceiver.
Increased data rates have motivated the investigation of advanced modulation schemes, such as four-level pulseamplitude modulation (PAM4), in optical interconnect systems in order to enable longer transmission distances and operation with reduced circuit bandwidth relative to non-return-to-zero (NRZ) modulation. Employing this modulation scheme in interconnect architectures based on high-Q silicon photonic microring resonator devices, which occupy small area and allow for inherent wavelength-division multiplexing (WDM), offers a promising solution to address the dramatic increase in datacenter and high-performance computing system I/O bandwidth demands. Two ring modulator device structures are proposed for PAM4 modulation, including a single phase shifter segment device driven with a multi-level PAM4 transmitter and a two-segment device driven by two simple NRZ (MSB/LSB) transmitters. Transmitter circuits which utilize segmented pulsed-cascode high swing output stages are presented for both device structures. Output stage segmentation is utilized in the single-segment device design for PAM4 voltage level control, while in the two-segment design it is used for both independent MSB/LSB voltage levels and impedance control for output eye skew compensation. The 65nm CMOS transmitters supply a 4.4V<sub>ppd</sub> output swing for 40Gb/s operation when driving depletion-mode microring modulators implemented in a 130nm SOI process, with the single- and two-segment designs achieving 3.04 and 4.38mW/Gb/s, respectively. A PAM4 optical receiver front-end is also described which employs a large input-stage feedback resistor transimpedance amplifier (TIA) cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity. Receiver linearity, critical in PAM4 systems, is achieved with a peak-detector-based automatic gain control (AGC) loop.
We report a 200 mm silicon photonic platform integrating a set of devices dedicated on HPC applications. PiN microring modulator layout and process are optimized together. Active tuning through heating section is investigated using either doped silicon or metal resistors. This technology is supported by a dedicated process design kit (PDK) compatible with conventional CMOS EDA tools. The PDK includes optical device models that will be described and compared with experimental results. A focus will be done on the PiN micro-ring modulator models which covering a wide range of geometries. DC mode and RF behaviors are supported.