This paper describes a differential readout circuit technique for uncooled Infrared Focal Plane Arrays (IRFPA) sensors.
The differential operation allows an efficient rejection of the common-mode noise during the biasing and readout of the
detectors. This has been enabled by utilizing a number of blind and thermally-isolated IR bolometers as reference
detectors. In addition, a pixel-wise detector calibration capability has been provided in order to allow efficient error
corrections using digital signal processing techniques. The readout circuit for a 64×64 test bolometer-array has been
designed in a standard 0.35-μm CMOS process. Circuit simulations show that the analog readout at 60 frames/s
consumes 30 mW from a 3.3-V supply and results in a noise equivalent temperature difference (NETD) of 125 mK for
The endurance of a FRAM is 1014 cycles with better retention times (>10 years). FRAM's have fast read/write access, low standby current, scalable and capable of ultra-low voltage operation. FRAM's share architectural features such as addressing schemes and I/O circuitry with other types of random access memories (DRAMs), but they have distinct features with respect to accessing the stored data, sensing, and overall circuit topology. The FRAM is a great advantage for SoC and wireless and mobile products, since it supports non-volatility but also delivers a fast memory access. Today's 1T/1C FRAM have an access time of 30 nS, a cycle time of 35 nS at 1.2 V power supply in a standard CMOS process with 2 mask adders. The cell size of a FRAM is comparable to that of a planar DRAM and is 3 - 4x denser than SRAM. This paper outlines the circuit innovations in embedded ferroelectric memories, and will cover the architecture, reference circuits, sense amplifiers, reliability issues and references to other memory technologies.
This paper explores the energy-delay space of eight widely referred flip-flops in a 0.13µm CMOS technology. The main goal has been to find the smallest set of flip-flop topologies to be included in a “high performance” flip-flop cell library covering a wide range of power-performance targets. Based on our comparison results, transmission gate-based flip-flops show the best power-performance trade-off with a total delay (clock-to-output + setup time) down to 105ps. For higher performance, the pulse-triggered flip-flops are the fastest (80ps) alternatives suitable to be included in a flip-flop cell library. However, pulse-triggered flip-flops consume significantly larger power (about 2.5x) compared to other fast but fully dynamic flip-flops such as TSPC and dynamic TG-based flip-flops.
Conference Committee Involvement (1)
Microelectronics: Design, Technology, and Packaging