Continuous shrinkage of design rule (DR) in ultra-large-scale integrated circuit (ULSI) devices brings about
greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction
of critical dimension (CD) tolerance for each object and budgeting the tolerance for each process step.
Furthermore, to extract adequate tolerance, design intent in terms of electrical behavior should be carefully
considered. Electrical behavior is carefully verified in design stages using various electronic design automation
(EDA) tools. However, once the design data is converted to layout data and signed off, most of the design intent is
abandoned and unrecognized in the process stage. Thus, instead of essential tolerance assignment according to
layout-related design intent, uniform and redundant tolerance is used, and so excess tolerance is assigned for some
layouts. To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent
speculation derived from design intent has been discussed. In this paper, test flow utilizing design intent
is developed. In the flow, electrical small-margin spots are extracted, verified with customized criteria according
to the tolerance derived from design intent, and fixed in the process. The proposed flow is examined and validated
for the application to 40nm node test chip.
As the technology node shrinks, printed-wafer shapes show progressively less similarity to the design-layout shapes, even with optical proximity correction (OPC). Design tools have a restricted ability to address this shape infidelity. Their understanding of lithography effects is limited, taking the form of design rules that try to prevent "Hot Spots" - locations that demonstrate wafer-printing problems. These design rules are becoming increasingly complex and therefore less useful in addressing the lithography challenges. Therefore, design tools that have a better understanding of lithography are becoming a necessity for technology nodes of 65 nm and below. The general goal of this work is to correct lithography Hot Spots during physical-design implementation. The specific goal is to automatically fix a majority of the Hot Spots in the Metal 2 layers and above, with a run time on the order of a few hours per layer. Three steps were taken to achieve this goal. First, Hot Spot detection was made faster by using rule-based detection. Second, Hot Spot correction was automated by using rule-based correction. Third, convergence of corrections was avoided by performing correction locally, which means that correcting one Hot Spot was very unlikely to create new Hot Spots.
A new design for manufacturability (DfM) scheme with a lithography compliance check (LCC) and hot spot fixing (HSF) flow has been developed to guarantee design compliance for OPC and RET by combining lithography simulator, hot spot detector and layout modification tool. Hot spots highlighted by the LCC flow are removed by the HSF flow following modification rule consists of "Line-Sizing" (LS) and "Space-Sizing (SS)" that are resize value of line-width and space-width for the original pattern. In order to meet layout modification requirements at the pre- and post- tape out (T.O.) stages, the priorities individually set for the modification rules and the design rules, which provides flexibly to achieve the modification scheme desirable at each stage. For handling large data at a fast speed, Layout Analyzer (LA) and Layout Optimizer (LO) engines were combined with the HSF flow. LA is used to reconstruct the original hierarchy structure, clips off small parts of the layout that include hot spots from the original layout and sends those to LO in order to reduce the computational time and resource. LO optimizes the clipped off layout following the prioritized modification- and design-rules. The new DfM scheme was found to be quite effective for hot spot cleaning for 65nm node and beyond, since it was demonstrated that the HSF flow improved the lithography margin for the metal layer of 65nm node full-chip data by reducing number of hot spots to below 0.1% of original within about 12 hours, using 1CPU of commercially available workstation.
As Technology node is advancing, we are forced to use relatively low resolution lithography tool. And these situation results in degradation of pattern fidelity. hot spot, lithographic margin-less spot, appears frequently by conventional design rule methodology. We propose two design rule methodology to manage hot spot appearances in the stage of physical pattern determination. One is restricted design rule, under which pattern variation is very limited, so hot spot generation can be fully controlled. Second is complex design rule combined with lithography compliance check (LCC) and hot spot fixing (HSF). Design rule, by itself, has a limited ability to reduce hot spot generation. To compensate the limited ability, both LCC including optical proximity correction and process simulation for detecting hot spots and HSF for fixing the detected hot spots are required. Implementing those methodology into design environment, hot spot management can be done by early stage of physical pattern determination. Also newly developed tool is introduced to help designers easily fixing hot spots. By using this tool, the system of automatic LCC and HSF has been constructed. hot spots-less physical patterns through this system can be easily obtained and turn-back from manufacture to design can be avoided.
Design and optical proximity correction (OPC) flow with hybrid OPC and manufacturability check (MC) tool was found to be effective for making robust pattern formation without any hot spots within feasible lead time under the low-k1 lithography condition. MC at design stage is essential for cleaning up hot spots in three ways; the refinement of design rule, the guideline for repairing hot spots for designers and the refinement of OPC deck. Hybrid OPC and MC tools with library- and model-based modules are available for reducing lead time by taking advantage of library system. Due to the design and OPC flow with the library-based OPC and MC tool, total lead time can be reduced to 55% of that in the case of conventional flow with MC. Assuming that a refined mask is ordered due to issue of hot spots without MC, the total lead time in the new flow can be reduced to 11% of that in the case of conventional technology.