Proc. SPIE. 6925, Design for Manufacturability through Design-Process Integration II
KEYWORDS: Optical lithography, Etching, Electroluminescence, Monte Carlo methods, Very large scale integration, Line width roughness, Transistors, Double patterning technology, Critical dimension metrology, Device simulation
To ensure the continuation of the scaling of VLSI circuits for years to come, the impact of litho on performance of logic
circuits has to be understood. Using different litho options such as single or double patterning may result in different
process variations. This paper evaluates the impact of litho variations on the yield of SRAM cells. The exploration is
focused on six transistor SRAM cells (6T SRAM) which have to be printed with the highest possible density with good
yield to limit system's cost. Consequently, these cells impose the most stringent constraints on litho techniques.
An SRAM cell is yielding if it operates correctly like a memory device (functional yield) and the performance of the
cell is in spec for the chosen architecture (parametric yield). In this paper, different metrics for the stability, readability
and write-ability are used to define parametric yield. The most important litho-induced variations are illumination dose,
focus, overlay mismatch and line-edge roughness. Unwanted opens and shorts in the printed patterns caused by the
process variations will cause the cell to malfunction. These litho-induced variations also cause dimension offsets, i.e.
variations on transistors' widths and lengths, which reduces the stability, readability and write-ability of the cell, thereby
increasing parametric yield loss.
Litho simulators are coupled with a device parasitic extractor to simulate the impact of the litho offsets on the yield of
the SRAM cell. Based on these simulations guidance will be provided on the choice between different litho options.
In this paper the impact of overlay and CD uniformity specifications on device and SRAM cell functional and
parametric yield are analyzed. The variation of channel strain due to partial etching of the stress layer is determined,
and we find that including this effect in the device parametric yield leads to severe CDU and overlay requirements. The
method is applied to SRAM cells and memories, and it is shown that only the co-optimization of SRAM cell layout,
CDU and overlay can increase the number of good dies per wafer.
The purpose of this paper is to use measurements on real working devices to derive more information than typically measured by the classic line-width measurement techniques.
The first part of the paper will discuss the principle of the measurements with a ring oscillator, a circuit used to measure the speed of elementary logic gates. These measurements contribute to the understanding of the exact timing dependencies in circuits, which is of utmost importance for the design and simulation of these circuits. When connecting an odd number of digital inverting stages in a ring, the circuit has no stable digital state but acts as an analog oscillator with the oscillation frequency dependent on the analog propagation delay of the signals through the stages. By varying some conditions during a litho step, the delay change caused by the process condition change can be measured very accurately. The response of the ring oscillator delay to exposure dose is measured and presented in this paper together with a comparison of measured line-width values of the poly gate lines.
The second part of the paper will focus on improving the intra-wafer variation of the stage delay. A number of ring oscillators are put in a design at different slit and scan locations. 200mm wafers are processed with 48 full dies present. From the intra-wafer delay fingerprint and the dose sensitivity of the delay an intra-wafer dose correction, also called a dose recipe, is calculated. This dose recipe is used on the scanner to compensate for effects that are the root cause for the delay profile; including reticle and processing such as track, etch and annealing.
A target of the 45nm node development at IMEC is to produce a working 6-transistor SRAM (6-T SRAM) cell. Here we describe the lithographic solutions for this challenge.
Following the requirements of the ITRS Roadmap requires challenging k<sub>1</sub> values. A classical 6-transistor SRAM design is difficult to scale to lower k1 values for imaging and overlay reasons. In this paper we discuss the litho friendly design that was used to originally produce a working 0.314μm<sup>2</sup> 45nm node 6-transistor SRAM cell. The design was scaled to a k<sub>1</sub> value of 0.31 for printing the active area layer on a 0.75NA ArF scanner at IMEC. Later on this was further scaled to a k<sub>1</sub> of 0.280 and a cell size of 0.274μm<sup>2</sup> for a working cell and imaging with a k<sub>1</sub> of 0.265 on a higher NA tool.
Various resolution enhancement techniques have been used for the three most critical layers of the SRAM cell: active area, poly gates and contact holes.
Although designed unidirectional, the active area and the poly layer of the SRAM cell have critical features in two directions and therefore choosing the right illuminator shape is not straightforward. A pupil shape optimizer was used to maximize the contrast of the aerial image of the various critical features in these layers.
For the contact layer the minimal pitch in the design is 160nm, which corresponds to a k<sub>1</sub> of 0.31. The pattern was split up into two images to increase the minimum pitch for the imaging to 190nm. Since off-axis illumination is used to print the 190nm pitch, assist features are added to the more sparse features. Contacts are not placed on a regular rectangular grid and additionally non-square contacts are used for local interconnects. This complicates the placement of the assist features and the interference mapping lithography (IML) technology was used to help in this task. The split design has been used in a double patterning approach in the SRAM process flow.
In this paper we show that all the above-mentioned resolution enhancement techniques have been successfully integrated and that it resulted in a working 45nm node SRAM cell.