The scaling-down evolution of semiconductor devices will ultimately attend fundamental limits as transistor reach the nanoscale aria. In this context the MOSFET models must give the process variations and the relevant characteristics like current, conductance, transconductance, capacitances, flicker thermal or high frequency noise and distortion. The new challenge of nanotechnology needs very accurate models for active devices. The design of linear analog circuits lacks models for state-of-the-art MOS transistors to accurately describe distortion effects. This is mainly due to inaccurate modelling of the mobility degradation effect i.e. the dependence of carrier mobility in the inversion layer on the gate
normal electric field. For short-channel devices the influence of series resistance becomes important and depends on the gate voltage. The drain current expression incorporating a new mobility relation obtained from quantum mechanical transport analysis and the series resistance influence is in good agreement with experiment.