LED wavelength and luminosity shifts due to temperature, dimming, aging, and binning uncertainty can cause large
color errors in open-loop light-mixing illuminators. Multispectral color light sensors combined with feedback circuits
can compensate for these LED shifts. Typical color light sensor design variables include the choice of light-sensing
material, filter configuration, and read-out circuitry. Cypress Semiconductor has designed and prototyped a color sensor
chip that consists of photodiode arrays connected to a I/F (Current to Frequency) converter. This architecture has been
chosen to achieve high dynamic range (~100dB) and provide flexibility for tailoring sensor response. Several different
optical filter configurations were evaluated in this prototype. The color-sensor chip was incorporated into an RGB light
color mixing system with closed-loop optical feedback. Color mixing accuracy was determined by calculating the
difference between (u',v') set point values and CIE coordinates measured with a reference colorimeter. A typical color
precision ▵u'v' less than 0.0055 has been demonstrated over a wide range of colors, a temperature range of 50C, and
light dimming up to 80%.
MEDUSA is the lightweight high resolution camera, designed to be operated from a solar-powered Unmanned Aerial
Vehicle (UAV) flying at stratospheric altitudes. The instrument is a technology demonstrator within the Pegasus program
and targets applications such as crisis management and cartography. A special wide swath CMOS imager has been
developed by Cypress Semiconductor Cooperation Belgium to meet the specific sensor requirements of MEDUSA.
The CMOS sensor has a stitched design comprising a panchromatic and color sensor on the same die. Each sensor
consists of 10000*1200 square pixels (5.5μm size, novel 6T architecture) with micro-lenses. The exposure is performed
by means of a high efficiency snapshot shutter. The sensor is able to operate at a rate of 30fps in full frame readout.
Due to a novel pixel design, the sensor has low dark leakage of the memory elements (PSNL) and low parasitic light
sensitivity (PLS). Still it maintains a relative high QE (Quantum efficiency) and a FF (fill factor) of over 65%. It features
an MTF (Modulation Transfer Function) higher than 60% at Nyquist frequency in both X and Y directions The measured
optical/electrical crosstalk (expressed as MTF) of this 5.5um pixel is state-of-the art. These properties makes it possible
to acquire sharp images also in low-light conditions.
The footprint of multi-transistor memory cell is limited by a complex connectivity layout. Depending on the architecture, the interconnect layers might be a hindrance in scaling the cell. This limitation is a result of the need for having multiple contacts to active or gate regions within small cell area as well as by the tight overlay requirements between these contacts and the overlaying metal. Minimum chrome line (i.e., contact space) CD of an attenuated phase shift mask used for printing these contacts as well as the mask and stepper alignment tolerances scale down slower than required by the technology roadmap. Moreover, the novel memory cell applications call for the increased cell complexity. In this work, we discuss how a combination of a new single damascene and self-aligned dual-damascene processes impact the area of a 6-Transistor Double-Wordline SRAM cell. We first identified the optimal cell architecture, followed by developing a unique interconnect scheme. In consequence, the area of the cell was reduced by as much as 25% within the 90 nm technology node. The new interconnect layer has been enabled at the expense of one additional mask.
Evolution of Optical Proximity Correction (OPC) methodology with the continuing shrink of feature size indicates a gradual shift towards increasingly more complex solutions, i.e., from rule based to model based OPC. The key underlying reason is to provide adequate accuracy ofpattern reproduction despite the growing sub-wavelength gap, i.e., the difference between minimum feature size and the wavelength used to print it [1 ]. However, full chip implementation of these complex solutions would increase CAD flow/mask generation runtimes and database file sizes, therefore compromising reticle manufacturability. In order to select optimal OPC routines based on feedback from process, CAD, design, and mask engineering, we proposed a methodology and investigated tradeoffs between correction accuracy and database complexity. Rule-based OPC, i.e., corrections defined by a set ofwidth and spacing proximity rules rely on a limited set oftest geometries and can't be made sensitive to the environment ofthe feature. In contrast, model based OPC features are generated for the actual layout environment and can be changed depending on the adopted photolithography process. Another degree of freedom is provided by the rule or model calibration. We defined and discussed complexity and accuracy criteria such as the size ofthe database and the number of silicon imaging errors.