The objective of this work is to study the possibility of implementing SOI rectennas for UWB RFIDs, with undoped Double Gate MOSFETs (DG-MOSFETs). For that purpose we use two commercial TCAD tools: Sentaurus Device (created by Synopsys), and ADS (created by Agilent) where in a large signal circuit model derived for the transistors is implemented with Verilog-A. Once the DG-MOSFETs output characteristics are fit, the rectennas performance at high frequencies is simulated; numerical and electrical results are successfully compared.
Variable capacitors, the varactors, are key components in many types of radiofrequency circuits and thus high quality
varactors are essential to achieve high quality factors in these devices.
This work presents results of a study on the variation of tuning range and quality factor when varying the depth and
separation of N+ diffusions in a PN junction varactor with fixed number of cells. For test needs four types of cells,
varying the geometry of N+ and P+ diffusions were designed. The varactors were formed by horizontally and vertically
overlapping cells. Based on their implementation structure, the varactors were divided into two groups, each comprising
4 varactors. The varactors belonging to the first group have all N+ diffusions connected to the buried layer. Varactors
from the second group use floating N+ diffusions and a buried N+ diffusion to separate pairs formed by two adjacent
Post implementation measurements show that the area of varactors from in the first and second group is 1795.74 μm2(51.9 x 34.6) and 1288.92 μm2 (46.7 x 27.6), respectively. The varactors from the 1st group have a high tuning range,
whereas the ones from the 2nd group high quality factors and require less area.
In this work, four different structures based on PN junction are studied. These structures are based on changing the
geometry of the p+ diffusion. The designed and fabricated devices will be used like integrated varactors in
radiofrequency applications. The measures have been made at frequencies since 500 MHz to 10 GHz, and the influence
that diffusion geometry has in the capacitance (C), the quality factor (Q) and the tuning range (TR) have been studied.
The pn varactors have been simulated with Taurus Device and have been fabricated in a 0.35um SiGe standard process.
In order to obtain better benefits of the varactors, the p+ and n+ diffusion geometries have been modified. This way, novel
structures called crosses, fingers, donuts, and bars have been designed and fabricated. The results of the tuning range
have been obtained superior to 40%.
The performance of stacked and miniature three-dimensional spiral inductors is analyzed and compared to standard
planar coils. For this purpose, nine of these new structures have been fabricated in a 0.35-μm four-metal SiGe process.
According to the measurement results, some of the proposed stacked inductors occupy only 48% of the area of a
conventional planar inductor with the same inductance value and work frequency. The area reduction is even more
significant with the miniature 3-D structures, which occupy only 22% in some cases, and translate the inductor self-resonance
frequency to higher values than the conventional stacked inductors. In spite of this area reduction, these new
structures employ metal levels close to the substrate, which significantly degrades the quality factor. So the standard
planar coils continue to be the best choice if the designer requires high-quality inductors. However, stacked and 3-D
miniature structures could be a better solution if the area saving is the circuit major priority.
This paper deals with the design and modeling of integrated spiral inductors for RF applications by means of a general purpose Electromagnetic (EM) simulator. These tools allow optimizing flexibly the inductor layout structure. The inductor performance can be obtained by using a three-dimensional design tool or a two-dimensional one. Planar 2-D or so called 2.5-Ds simulators are faster and accept complex coil geometries. We have used one of these simulators, the Advanced Design System planar EM simulator, Momentum, from Agilent.
The inductor quality factor (Q) is limited, among other phenomena, by the series resistance of the metal traces and the substrate losses. Therefore the simulator requires an accurate set up of the process and simulator parameters and a correct algorithm to model metal thickness to rely on simulation results. In this paper we analyze and compare these different approaches.
A high-quality factor inductor library on a 0.35 μm SiGe technology at 5 GHz is also designed in this work using the proper simulator set up. Nine of the inductors have been fabricated and measured to test the simulator reliability. Measurements taken over a frequency range from 500 MHz to 10GHz show a good agreement with 2.5-EM simulations.
In this paper models for the capacitance of cross integrated varactors based in the PN junction are presented. Three different approximations are assumed, in order to reproduce the measured results of the capacitance. The relative error with the measured capacitance is under 10% in all cases.
Integrated inductors are key components in Radio Frequency Integrated Circuits (RFICs) because they are needed in several building blocks, such as voltage-controlled oscillators (VCOs), low-noise amplifiers (LNAs), mixers, or filters. The cost reduction, achieved in the circuit assemblage, makes them preferable to Surface Mounted Devices in spite of the different sources of lost that limits the use of integrated inductors; there are losses associated with the semiconductor substrate, and losses in the metals. We report, in this work, our research in modeling integrated inductors, particularly the losses in the metals. The model is derived from measurements taken from integrated spiral inductors designed and fabricated in a standard silicon process. The measurements reveal that the widely accepted lumped equivalent model does not properly predict the integrated inductor behavior at frequencies above 3 GHz for our technology. We propose a simple modification in the lumped equivalent circuit model: the introduction of an empirical resistor in the port 1-to-port 2 branch of the equivalent circuit. As a result, it will be demonstrated that the integrated inductor behavior is adequately predicted in a wider frequency range than does the conventional model. We also report a new methodology for characterizing the integrated inductors including the new resistor. In addition, the new model is used to build-up an integrated inductor library containing optimized integrated inductors.
This work analyses the DC response of an InGaAs channel PHFET when varying temperature. An analytic model for the drain current is derived from previous work, incorporating the extrinsic resistances. Experimental output characteristics at different temperatures are compared with those offered by the resulting model and numerical simulations. The DC drain current is obtained introducing the external voltages applied to the HFET terminals into an intrinsic model. The temperature range considered in this paper is between 300 and 400 K. In this range, the temperature dependence of the intrinsic electrical parameters is included in the model. For the temperature dependence of the extrinsic resistances, the HFET is numerically simulated with MINIMOS-NT. As far as we know, any influence of the electron transport through the AlGaAs/InGaAs heterojunction on the extrinsic resistances has not been already established. In our case, a termionic-field-emission (TFE) is used to simulate this effect (without TFE not only the drain current is underestimated, but also the temperature dependence predicted is opposite to the actual).
As result, the extrinsic source resistence is nearly constant (7.5 ohms), and higher values are obtained for the extrinsic drain resistence, which has a linear and positive temperature dependence, raising as the transistor operates in saturation region. When the drain voltage diminishes, the influence of the TFE model on the extrinsic resistances vanishes, and RD tends to RS. The drain current predicted by the model, in linear and saturation region, shows a relative error between measured and modeled values smaller than 10%.