In this paper, we describe a framework to enable the memory array simulations for Materials to Systems CooptimizationTM (MSCOTM) flows. The methodology is applied for projected 3 nm logic FinFET technology node SRAM array. To form the SRAM array, a “tiling” approach is utilized, where neighbor cells are created by copying and mirroring the first cell. Then this process is repeated to create the rest of the array. Electrical pulses are applied to the word-line and bit-line to activate the read and write operations. We demonstrate 128 ×128 SRAM array simulations and find that the farthest cell from the word-line driver is vulnerable.