Benjamin Duclaux
Staff Engineer at STMicroelectronics (Crolles II) SAS
SPIE Involvement:
Profile Summary

Senior Lithography Research and Development Engineer, working at STMicroelectronics in Crolles (France). Was assignee at Albany (NY) Nanotech center within IBM-GF-Samsung and STMicro alliance. Worked on Lithography process development from 40nm to 7nm logic nodes as well as imaging technology. Now focusing on Overlay and APC for advance fabs.
Publications (4)

Proceedings Article | 27 April 2023 Poster + Paper
Proceedings Volume 12496, 1249627 (2023)
KEYWORDS: Scanners, Advanced process control, Mathematical optimization, Overlay metrology, Feedback loops, Process modeling, Lithography

Proceedings Article | 20 March 2020 Presentation + Paper
Proceedings Volume 11325, 113251K (2020)
KEYWORDS: Semiconducting wafers, Overlay metrology, Reticles, Scanners, Metrology, Data modeling, Sensors, Data corrections, Process modeling, Performance modeling, Lithographic process control

Proceedings Article | 20 March 2020 Paper
Proceedings Volume 11325, 113251W (2020)
KEYWORDS: Etching, Semiconducting wafers, Scanners, Overlay metrology, Contamination, Lithography, Plasma

Proceedings Article | 13 March 2018 Presentation + Paper
Proceedings Volume 10585, 105851C (2018)
KEYWORDS: Overlay metrology, Optical alignment, Scanners, Process control, Data modeling, Reticles, Reliability, Optical lithography

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