Senior Lithography Research and Development Engineer, working at STMicroelectronics in Crolles (France). Was assignee at Albany (NY) Nanotech center within IBM-GF-Samsung and STMicro alliance. Worked on Lithography process development from 40nm to 7nm logic nodes as well as imaging technology. Now focusing on Overlay and APC for advance fabs.
Run to run and model variability of overlay high order process corrections for mean intrafield signatures