As the industry progresses toward smaller patterning nodes with tighter CD error budgets and narrower process
windows, the ability to control pattern quality becomes a critical, yield-limiting factor. In addition, as the feature size of
design layouts continues to decrease at 32nm and below, optical proximity correction (OPC) technology becomes more
complex and more difficult. From a lithographic point of view, it is the most important that the patterns are printed as
designed. However, unfavorable localized CD variation can be induced by the lithography process, which will cause
catastrophic patterning failures (i.e. ripple effects, and severe necking or bridging phenomenon) through process
variation. It is becoming even more severe with strong off-axis illumination conditions and other resolution enhancement
techniques (RETs). Traditionally, it can be reduced by optimizing the rule based edge fragmentation in the OPC setup,
but this fragmentation optimization is very dependent upon the engineer's skill. Most fragmentation is based on a set of
simple rules, but those rules may not always be robust in every possible design shape.
In this paper, a model based approach for solving these imaging distortions has been tested as opposed to a previous
rule based one. The model based approach is automatic correction techniques for reducing complexity of the OPC recipe.
This comes in the form of automatically adjusting fragments lengths along with feedback values at every OPC iterations
for a better convergence. The stability and coverage for this model based approach has been tested throughout various
In double-patterning technology (DPT), we study the complex interactions of layout creation, physical design and design
rule checking flows for the 22nm and 16nm device nodes. Decomposition includes the cutting (splitting) of original
design-intent features into new overlapping polygons where required; and the coloring of all the resulting polygons into
two mask layouts. We discuss the advantages of geometric distribution for polygon operations with the limited range of
influence. Further, we find that even the naturally global coloring step can be handled in a geometrically local manner.
We analyze and compare the latest methods for designing, processing and verifying DPT methods including the 22nm
and 16nm nodes.
A variety of innovations including the reduction of actinic wavelength, an increase in lens NA, an
introduction of immersion process, and an aggressive OPC/RET technique have enabled device shrinkage
down to the current 45nm node. The immaturity of EUV and high index immersion, have made logic
manufacturers look at other ways of leveraging existing exposure technologies as they strive to develop
process technology for 32nm and below. For design rules for sub-nodes from 32nm to 22nm, the need to
define critical layers with double photolithography and etch process becomes increasingly evident.
Double patterning can come in a variety of forms or 'flavors'. For 32/28nm node, the patterning of 2D
features is so challenging that opposing line-ends can only be defined using an additional litho and etch
step to cut them. For 22nm node, even line/space gratings are below the theoretical k1=0.25 imaging limit.
Therefore pitch-doubling double patterning decomposition is absolutely required. Each double patterning
technology has its own set of challenges. Most of all, an existing design often cannot be shrunk blindly and
then successfully decomposed, so an additional set of restrictions is required to make layouts double
patterning compliant. To decompose a logic layout into two masks, polygons often need to be cut so that
they can be patterned using both masks. The electric performance of this cut circuitry may be highly
dependent on the quality of layout decomposition, the circuit characteristics and its sensitivity to
misalignment between the two patterning steps. We used representative logic layouts of metal level and
realistic models to demonstrate the issues involved and attempt to define formal rules to help enable lineend
splitting and pitch-doubling double patterning decomposition. This study used a variety of shrink
approaches to existing legacy layouts to evaluate double patterning compliance and a careful set-up of
parameters for the pitch splitting decomposition engine. The quality of the resultant imaging was tuned
using double patterning aware OPC and printability verification tools.
Metal layers have some drawbacks in building up model based OPC (MBOPC) because metal layers are mainly
composed of 2 dimensional (2D) patterns which show modeling inaccuracy and the difficulty of fragment optimization
compared with 1-dimensional patterns. As a result, metal layers have considerable hot spots such as pinch, bridge and
insufficient contact overlap. The modeling inaccuracy of 2D patterns results from a few reasons like measurement noise,
inaccurate optical simulation and empirical resist modeling etc. The fragment optimization operated by rule does not
control automatically corner rounding problems induced by small jogs of 2D patterns. The design for manufacturability
(DFM) is known to provide a solution to overcome these problems. One of engines operating the DFM is MBOPC,
which is made by an empirical process model and offers the process variation counter map simulated by the MBOPC
engine. However, the accuracy of the simulation is quite low because we cannot avoid over-corrected patterns generated
inevitably with the empirical model. In order to detect and correct the hot spots caused by the design itself, that is, the
inherent function of the DFM, it is necessary to provide the OPC engine of the physical model with the optimized
illumination condition to rule out empirical effect. Physical model is more emphasized in case of process window
simulation because of its accuracy in the edge boundary of process window. One of important function of DFM for the
metal layers is to enhance the contact overlap margin which can be influenced by the lithography process such as line
end shortening, corner rounding effect and miss-alignment. Etch process is also a significant parameter of contact
overlap. Calibrated process model is very effective to detect the insufficient contact overlap with process window.
In this paper, MBOPC of sub-45nm node metal layers is studied to provide the effective DFM engine. The DFM flow
with renewed MBOPC engine will show the improved process window and large contact overlap margin and will also
make it possible to search and correct just patterns capable of decreasing the process window by only layout defect itself.
Since the sub-50nm logic lithography approaches to k1 value of 0.3, it seems to be an impossible task to print typical
logic patterns composed of random shapes and mixed pitches using the conventional resolution enhancement technology
(RET). As one of the effective solutions to deal well with this issue, lithography friendly design (LFD) and advanced
optical proximity correction (OPC) technology have been considered and developed. However, the investigation on the
distortion types of various 2-dimensional patterns has rarely been preceded up to now, while lithographical hot spots are
observed are dominated by the 2-dimensional patterns rather than in the 1-dimensional patterns. In order to provide a
LFD layout and a good OPC performance for the future node logic device, the analysis and the hot spot's classification
of the 2-dimensional pattern need to be performed. Based on our analysis of various pattern types at mimic-logic test
block, a feedback strategy was implemented to reduce the 2-dimensional hot spots through the correction stage of the
OPC recipes. In our study, we find out the proper value of ground rule and the cost-effective methodology which should
go with reciprocal encouragement in OPC and LFD. This will give us a good methodology for the lithography
technology nodes and upstream design for manufacturability (DFM) approaches.