This will count as one of your downloads.
You will have access to both the presentation and article (if available).
Silicon-on-insulator (SOI) substrate technology has been the defining foundation of silicon photonics integrated circuits over the last 20+ years, fostering its commercial success in datacenter interconnects and promoting widespread adoption for high-speed optical transceiver products. More recently, novel applications could also leverage the silicon photonics toolset and ecosystem maturity to target newer, expanding markets, including consumer sensing for healthcare monitoring devices, LiDAR devices for the automotive, as well as optics-based advanced quantum computing and neural networks.
In such dynamic context, Photonics-SOI substrates design and the underlying Smart-Cut process need to relentlessly adapt in order to meet the evolving requirements of end-products and applications specifications, while addressing industrial high-volume manufacturability, high fabrication yields, cost-effectiveness, and related quality constraints. More specifically, the need for growing aggregated bandwidth density at low power dissipation in transceivers products as well as the integration of increasingly complex optical functions for sensing applications, are driving towards more stringent requirements in terms of top silicon layer within-wafer and wafer-to-wafer uniformity, atomic-scale surface roughness, low defect density and improved crystalline material quality. In this paper, the authors report on technological advances in the 300-mm Photonics-SOI process, while benchmarking these on a 300-mm silicon photonics multi-project wafer (MPW) process run. Notably, an extensive set of silicon photonics devices and circuits will be fabricated on a matrix of 220-nm-thick 2-μm-buried oxide Photonics-SOI substrates using different Smart-Cut process windows, with optical characterization data and device performance supporting the ultimate choice of substrate technology for silicon photonics process design kits on thin-SOI platforms.
In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive electro-optic characterization of these components will be presented.
View contact details
No SPIE Account? Create one
