Dr. Bhanwar Singh Profile

Dr. Bhanwar Singh

CEO at Mobi Venture Inc

SPIE Involvement:

Track Chair | Author

Publications (34)

Proceedings Article | 5 April 2007 Paper

Across-wafer CD uniformity control through lithography and etch process: experimental verification

Qiaolin Zhang, Cherry Tang, Jason Cain, Angela Hui, Tony Hsieh, Nick Maccrae, Bhanwar Singh, Kameshwar Poolla, Costas Spanos

Proceedings Volume 6518, 65182C (2007) https://doi.org/10.1117/12.711232

KEYWORDS: Etching, Critical dimension metrology, Plasma etching, Semiconducting wafers, Process control, Plasma, Lithography, Picosecond phenomena, Metrology, Temperature metrology

Read Abstract +

Proceedings Article | 5 April 2007 Paper

Realizing "value-added" metrology

Benjamin Bunday, Pete Lipscomb, John Allgair, Dilip Patel, Mark Caldwell, Eric Solecky, Chas Archie, Jennifer Morningstar, Bryan Rice, Bhanwar Singh, Jason Cain, Iraj Emami, Bill Banke, Alfredo Herrera, Vladamir Ukraintsev, Jerry Schlessinger, Jeff Ritchison

Proceedings Volume 6518, 65181K (2007) https://doi.org/10.1117/12.714216

KEYWORDS: Metrology, Overlay metrology, Inspection, Semiconducting wafers, Process control, Yield improvement, Critical dimension metrology, Optical proximity correction, Etching, Lithography

Read Abstract +

The conventional premise that metrology is a "non-value-added necessary evil" is a misleading and dangerous assertion, which must be viewed as obsolete thinking. Many metrology applications are key enablers to traditionally labeled "value-added" processing steps in lithography and etch, such that they can be considered integral parts of the processes. Various key trends in modern, state-of-the-art processing such as optical proximity correction (OPC), design for manufacturability (DFM), and advanced process control (APC) are based, at their hearts, on the assumption of fine-tuned metrology, in terms of uncertainty and accuracy. These trends are vehicles where metrology thus has large opportunities to create value through the engineering of tight and targetable process distributions. Such distributions make possible predictability in speed-sorts and in other parameters, which results in high-end product. Additionally, significant reliance has also been placed on defect metrology to predict, improve, and reduce yield variability. The necessary quality metrology is strongly influenced by not only the choice of equipment, but also the quality application of these tools in a production environment. The ultimate value added by metrology is a result of quality tools run by a quality metrology team using quality practices. This paper will explore the relationships among present and future trends and challenges in metrology, including equipment, key applications, and metrology deployment in the manufacturing flow. Of key importance are metrology personnel, with their expertise, practices, and metrics in achieving and maintaining the required level of metrology performance, including where precision, matching, and accuracy fit into these considerations. The value of metrology will be demonstrated to have shifted to "key enabler of large revenues," debunking the out-of-date premise that metrology is "non-value-added." Examples used will be from critical dimension (CD) metrology, overlay, films, and defect metrology.

Proceedings Article | 27 March 2006 Paper

Advanced DFM applications using design-based metrology on CD SEM

G. Lorusso, L. Capodieci, D. Stoler, B. Schulz, S. Roling, J. Schramm, C. Tabery, K. Shah, B. Singh, G. Abbott, A. Roberts, A. Azordegan, L. Heinrichs, Z. Kaliblotzky, E. Castel

Proceedings Volume 6152, 61520B (2006) https://doi.org/10.1117/12.674776

KEYWORDS: Semiconducting wafers, Metrology, Optical proximity correction, Pattern recognition, Design for manufacturing, Scanning electron microscopy, Calibration, Computer aided design, Resolution enhancement technologies, Algorithm development

Read Abstract +

Proceedings Article | 15 March 2006 Paper

Combined use of x-ray reflectometry and spectroscopic ellipsometry for characterization of thin film optical properties

Jason Cain, Stephen Robie, Qiaolin Zhang, Bhanwar Singh, Iraj Emami

Proceedings Volume 6155, 61550P (2006) https://doi.org/10.1117/12.660088

KEYWORDS: Optical properties, Thin films, Ellipsometry, Data modeling, Oscillators, X-rays, Spectroscopic ellipsometry, Reflectometry, Silicon, Semiconducting wafers

Read Abstract +

Proceedings Article | 12 May 2005 Paper

Characterization, modeling, and impact of scattered light in low-k1 lithography

Bruno La Fontaine, Yunfei Deng, Mircea Dusa, Alden Acheta, Anita Fumar-Pici, Harish Bolla, Beverly Cheung, Bhanwar Singh, Harry Levinson

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.601188

KEYWORDS: Modulation transfer functions, Scanners, Light scattering, Lithography, Spatial frequencies, Scatterometry, Critical dimension metrology, Computer simulations, Semiconducting wafers, Optical microscopes

Read Abstract +

Proceedings Article | 10 May 2005 Paper

Comprehensive CD uniformity control across lithography and etch

Qiaolin Zhang, Cherry Tang, Tony Hsieh, Nick Maccrae, Bhanwar Singh, Kameshwar Poolla, Costas Spanos

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.601087

KEYWORDS: Critical dimension metrology, Plasma, Plasma etching, Etching, Control systems, Semiconducting wafers, Lithography, Temperature metrology, Oxygen, Process control

Read Abstract +

Proceedings Article | 10 May 2005 Paper

Design-based metrology: advanced automation for CD-SEM recipe generation

C. Tabery, L. Capodieci, C. Haidinyak, K. Shah, M. Threefoot, B. Choo, B. Singh, Y. Nehmadi, C. Ofek, O. Menadeva, A. Ben-Porath

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.601143

KEYWORDS: Optical proximity correction, Metrology, Computer aided design, Semiconducting wafers, Resolution enhancement technologies, Reticles, Calibration, Photomasks, Scanning electron microscopy, Data modeling

Read Abstract +

The procedure for properly implementing OPC for a new technology node or chip design involves multiple steps: selection of the RET (resolution enhance technique), selection of design rules, OPC Model Building, OPC Verification, CD control quantification (across chip, reticle, wafer, focus, exposure, etc), calibration of Optical Rule Checks (ORC), and other verification steps. Many of these steps require up to thousands of wafer measurements, and while state-of-the-art CD-SEM tools provide automated metrology for production, manually creating a CD recipe with thousands of unique sites is extremely tedious and error-prone. This places a practical limit on both the quality and number of measurements that can be acquired during the technology development and qualification period. At the same time, the number of measurements required to qualify a new reticle design has increased drastically due to the growing complexity of RET and diminishing tolerances. To meet this challenge, a direct and automated link from the design systems to the process metrology tools is needed. Novel methodologies must also be developed to enable automated generation of teh recipe from the design inputs and to translate the flood of metrology results into information that can improve the design, mask data processing, or the patterning process. To facilitate this two-way data flow, a new framework has been created enabling true Design-Based Metrology (DBM), and an application named OPC-Check has been developed to operate within this framework. This DBM framework provides the common language and interface that facilitates the direct transfer of desired measurement locations from teh design to the metrology tool. This link is a critical element in Design for Manufacturability (DFM) efforts, a central theme in many presentations at Microlithography 2005. This article discusses the significant benefits of the tight integration of design and process metrology for OPC implementation in a new technology node, and provides some examples of the novel OPC-Check application as currently implemented at AMD SDC with Applied Materials CD-SEM tools.

Proceedings Article | 24 May 2004 Paper

Across-wafer CD uniformity enhancement through control of multizone PEB profiles

Qiaolin Zhang, Paul Friedberg, Cherry Tang, Bhanwar Singh, Kameshwar Poolla, Costas Spanos

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.537121

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Data modeling, Temperature metrology, Control systems, Lithography, Etching, Metrology, Process control, Thermal modeling

Read Abstract +

Proceedings Article | 24 May 2004 Paper

Time-based PEB adjustment for optimizing CD distributions

Paul Friedberg, Cherry Tang, Bhanwar Singh, Thomas Brueckner, Wolfram Gruendke, Bernd Schulz, Costas Spanos

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.535871

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Temperature metrology, 193nm lithography, Photoresist materials, Scatterometry, Data modeling, Lithography, Sensors, Thermal effects

Read Abstract +

Proceedings Article | 29 April 2004 Paper

Intra-wafer CDU characterization to determine process and focus contributions based on scatterometry metrology

Mircea Dusa, Richard Moerman, Bhanwar Singh, Paul Friedberg, Ray Hoobler, Terry Zavecs

Proceedings Volume 5378, (2004) https://doi.org/10.1117/12.543786

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Lithography, Metrology, Error analysis, Scatterometry, Reticles, Photoresist processing, Statistical analysis, Finite element methods

Read Abstract +

Current advanced lithography processes are based on a Critical Dimension (CD) budget of 10nm or less with errors caused by exposure tool, wafer substrate, wafer process, and reticle. As such, allowable CD variation across wafer becomes an important parameter to understand, control and minimize. Three sources of errors have an effect on CD Uniformity (CDU) budget, run-to-run (R2R), wafer-to-wafer (W2W) and intra-wafer. While R2R and W2W components are characterized and compensation conrol techniques were developed to minimize their contribution the intra-wafer component is more or less ignored with the consequence that its sources of errors have not been characterized and no compensation technique is available. In this paper, we propose an approach to analyze intra-wafer CD sources of variations identifying the non-random CDU behavior and connect this with disturbances caused by processing errors described by their wafer spatial coordinates. We defined a process error as disturbance and its effect as a feature response. We study the impact of modeling spatial distribution of a feature response as calculated by diffractive optical CD metrology (scatterometry) and relate it to a programmed process disturbance. Process disturbances are classified in terms of time characteristics that define their spatial distribution. We demonstrated feature response to a disturbance behavior as statistical values as well as spatial profile. We identified that CD response is not sufficient to determine the sources of process disturbance and accordingly added responses from other features, which add to detection of CDU sources of error. The added respsonses came from scatterometry principle based on model difinition of a litho patter described by its shape with characteristic features: bottom CD, resist thickness, sidewall angle and bottom antireflective layer thickness. Our results show that process errors with continuous intra-wafer variation, such as PEB and BARC thickness have larger effects on CDU compared to process errors with discrete intra-wafer behavior, such as dose and defocus. Correlation between multiple feature responses to process disturbance was characterized as spatial covariance between CD to resist thickness and CD to SWA. Spatial feature covariance enhances capability to infer sources of process disturbance from metrology data.

Proceedings Article | 2 June 2003 Paper

Scatterometry-based overlay metrology

Hsu-Ting Huang, Gayathri Raghavendra, Apo Sezginer, Kenneth Johnson, Fred Stanke, Michelle Zimmerman, Cristina Cheung, Makoto Miyagi, Bhanwar Singh

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483668

KEYWORDS: Overlay metrology, Scatterometry, Reticles, Semiconducting wafers, Photomasks, Optical properties, Diffraction gratings, Metals, Scatter measurement, Diffraction

Read Abstract +

Proceedings Article | 16 July 2002 Paper

Characterizing post-exposure bake processing for transient- and steady-state conditions, in the context of critical dimension control

David Steele, Anthony Coniglio, Cherry Tang, Bhanwar Singh, Steve Nip, Costas Spanos

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473491

KEYWORDS: Semiconducting wafers, Sensors, Critical dimension metrology, Photoresist materials, Temperature metrology, Optical lithography, Wafer testing, Photoresist developing, Silicon, Deep ultraviolet

Read Abstract +

The Post-Exposure Bake (PEB) is one of the critical pattern transfer steps in deep ultra-violet 248nm, 193nm (DUV) photolithography. The objective of the PEB is to activate the photo-acid produced during the exposure, which, in a self-catalyzing sequence, attacks the bonds of the organic compounds within the resist, making them soluble to the developer solution. This sequence generates more photo-acid, and the cycle continues until the process self-quenches. The acid is also rapidly diffusing along its concentration gradients, further impacting the final dimensions of the resulting pattern. All these phenomena are very sensitive to the PEB temperature trajectory, especially during the early stages of the process. Using existing state of the art equipment calibrated specifically to measure PEB effects, it has been reported that as much as 30 percent of the critical dimension (CD) error budget is due to the PEB variations from plate to plate or across one plate. Virtually all practical PEB procedures call for the rapid heating of the wafer to a recommended target temperature and time, followed by the rapid cooling down to near room temperature. The temperature and timing of the PEB and subsequent cooling are optimized for the particular photoresist chosen for processing. Due to the transient nature of the post exposure bake, aspects such as time-to-temperature, temperature overshoot, as well as steady-sate behavior must be measured, understood, and optimized in order to improve CD control, while minimizing, and if necessary, accommodating any variation across the PEB plate. Until recently, reliable measurements of the actual PEB temperature trajectories have been difficult to obtain. The PEB temperature mapping system provided by OnWafer Technologies allows for these conditions, since it is capable of processing inside the lithography track system as if it were a product wafer due to its design and its wireless nature. Furthermore, it has more than 40 rapid response sensors spread across the wafer surface, and thermal mass close to that of a product wafer. In this way, it can collect the temperature as a function of time during loading, transporting, heating and cooling, and it can provide an accurate view of the thermal history across the surface of a wafer. This information, coupled with physical models of the equipment and of the process can be used to more accurately characterize PEB behavior and its impact in CD control. Experiments done to date using the OnWafer system confirm that typical PEB steps can be too short for reaching steady-state conditions. More specifically, state of the art bake plates were found to require several seconds to heat a typical wafer within a degree of the target temperature, and they can overshoot the target temperature by a degree or more. Moreover, these plates may need a few minutes to stabilize within 0.1 degrees C from that target. Similar time constants apply during the cooling sequence. Experiments involving detailed gate layer CD measurements further validate the hypothesis that transient effects are responsible for much of the CD errors due to PEB, especially since these transient effects have a traceable non-uniformity. This paper will highlight the metrology involved in detecting PEB non-uniformities, demonstrate how the results of real-time post exposure bake data collection differ from 'static bake data test' collection and provide in-line bake data alongside collected CD data.

Proceedings Article | 18 August 2000 Paper

Automated OPC optimization using in-line CD-SEM

Bo Su, Mina Menaker, Nadav Haas, Ramkumar Subramanian, Bhanwar Singh

Proceedings Volume 4181, (2000) https://doi.org/10.1117/12.395714

KEYWORDS: Optical proximity correction, Photomasks, Semiconducting wafers, Wafer testing, Resolution enhancement technologies, Optical lithography, Printing, Lithography, Scanning electron microscopy, Optimization (mathematics)

Read Abstract +

Proceedings Article | 2 June 2000 Paper

Improving stigmation control of the CD-SEM

Bryan Choo, Shobhana Punjabi, Carmen Morales, Bhanwar Singh, Michael Templeton, Mark Davidson

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386460

KEYWORDS: Scanning electron microscopy, Electron beams, Critical dimension metrology, Optical alignment, Image quality, Chlorine, Metrology, Image resolution, Lithography, Etching

Read Abstract +

Proceedings Article | 2 June 2000 Paper

Optical characterization in the vacuum ultraviolet with variable angle spectroscopic ellipsometry: 157 nm and below

James Hilfiker, Bhanwar Singh, Ron Synowicki, Corey Bungay

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386495

KEYWORDS: Refractive index, Thin films, Vacuum ultraviolet, Lithography, Silicon, Silicon films, Spectroscopic ellipsometry, Optical properties, Photoresist materials, Dielectrics

Read Abstract +

Proceedings Article | 2 June 2000 Paper

Impact of optical absorption on process control for sub-0.15-nm device patterning using 193-nm lithography

Uzodinma Okoroanyanwu, Harry Levinson, Jeremias Romero, Bhanwar Singh, Shih-Jung Lee

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386537

KEYWORDS: Absorption, Critical dimension metrology, Lithography, Process control, Reflectivity, Silicon, Optical lithography, Photoresist materials, Semiconducting wafers, Refractive index

Read Abstract +

Proceedings Article | 2 June 2000 Paper

Process control and optimization of conventional metal process for 0.18-micron logic technology

Ramkumar Subramanian, Stuart Brown, Susan Chen, Carmen Morales, Ernesto Gallardo, Bhanwar Singh

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386470

KEYWORDS: Critical dimension metrology, Metals, Oxides, Reflectivity, Process control, Optical lithography, Tin, Semiconducting wafers, Deep ultraviolet, Lithography

Read Abstract +

Proceedings Article | 2 June 2000 Paper

Automated process control monitor for 0.18-um technology and beyond

Bryan Choo, Trina Riley, Bernd Schulz, Bhanwar Singh

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386474

KEYWORDS: Line scan image sensors, Critical dimension metrology, Semiconducting wafers, Process control, Lithography, Image processing, Pattern recognition, Etching, Lithium, Optical lithography

Read Abstract +

Currently, most production fabs use critical dimension (CD) measurements as their primary means for process control in printing lines, spaces and contacts. Historically, this has been adequate to control the lithography and etch processes and produce reasonable yields. However, as the industry moves from 0.25 micrometer manufacturing to 0.18 micrometer and beyond, it is becoming increasingly obvious that CD measurements alone do not provide enough information about the printed structures. As the geometry shrinks, slight changes in the shape and profile can significantly affect the electrical characteristics of the circuit while maintaining the same CD value. In this paper, we will describe a method which, in conjunction with the CD measurements, better characterizes the circuit structures and therefore provides valuable feedback about the process. This method compares stored image and linescan information of a 'golden' (correctly processed) structure to that of the structure being measured. Based on the collected data, it is possible to distinguish between different profiles and determine if a process shift has occurred, even when the measured CD remains within specification. The correlation score therefore provides an additional constraint that better defines the true process window and provides an additional flag for process problems. Without this information, the process used may not be truly optimized, or a shift may occur that is not detected in a timely manner, resulting in the loss of yield and revenue. This data collection has been implemented in production on a local interconnect lithography process. Before the correlation information was available, it was very difficult to detect the scumming within the LI trench, in which it was a time consuming and labor intensive procedure to identify problem lots. The correlation scores, collected automatically and concurrently with the CD measurement, allowed tracking through the SPC chart and the automatic flagging of problems while the lot was still in the photolithography module. The result has been faster feedback control and thus less scrap material.

Proceedings Article | 2 June 2000 Paper

Specular spectroscopic profilometry for the sub-0.18-um polySi-gate processes

Xinhui Niu, Nickhil Jakatdar, Sanjay Yedur, Bhanwar Singh

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386449

KEYWORDS: Spectroscopy, Metrology, Diffraction, Lithography, Diffraction gratings, Etching, Thin films, Spectroscopes, Deep ultraviolet, Atomic force microscopy

Read Abstract +

Proceedings Article | 14 June 1999 Paper

Evaluation of atomic force microscopy: comparison with electrical CD metrology and low-voltage scanning electron microscopy

Sanjay Yedur, Bhanwar Singh

Proceedings Volume 3677, (1999) https://doi.org/10.1117/12.350853

KEYWORDS: Critical dimension metrology, Atomic force microscopy, Scanning electron microscopy, Metrology, Environmental sensing, Semiconducting wafers, Atomic force microscope, Resistors, Cadmium, Reliability

Read Abstract +

Proceedings Article | 4 September 1998 Paper

Sub-100-nm and deep sub-100-nm MOS transistor gate patterning

Qi Xiang, Subash Gupta, Chris Spence, Bhanwar Singh, Geoffrey Yeap, Ming-Ren Lin

Proceedings Volume 3506, (1998) https://doi.org/10.1117/12.323977

KEYWORDS: Etching, Transistors, Oxides, Optical lithography, Metrology, Scanning electron microscopy, Lithography, Molybdenum, Deep ultraviolet, Photoresist materials

Read Abstract +

Proceedings Article | 29 June 1998 Paper

Deep-UV reflection control for patterning dielectric layers

Ramkumar Subramanian, Gurjeet Bains, Christopher Lyons, Bhanwar Singh, Ernesto Gallardo

Proceedings Volume 3334, (1998) https://doi.org/10.1117/12.310765

KEYWORDS: Semiconducting wafers, Etching, Dielectrics, Reflection, Reflectivity, Deep ultraviolet, Optical lithography, Critical dimension metrology, Oxides, Standards development

Read Abstract +

Proceedings Article | 8 June 1998 Paper

Efficient and cost-effective photo defect monitoring

Khoi Phan, Robert Chiu, Shobhana Punjabi, Bhanwar Singh

Proceedings Volume 3332, (1998) https://doi.org/10.1117/12.308785

KEYWORDS: Semiconducting wafers, Oxides, Wafer testing, Silicon, Photoresist processing, Defect detection, Particles, Inspection, Deep ultraviolet, Manufacturing

Read Abstract +

Manufacturing processes for submicron integrated circuits require strict process control for minimizing defects during the fabrication process. Defect densities are monitored on product wafers to determine whether the line maintains an acceptable yield level and to prevent any catastrophic downfall. However, defect detection is difficult for multilayer devices. A short loop defect monitor is often employed in the Photolithography area for inspection on an automated wafer inspection system like the KLA 213x. This monitor usually uses clean bare Silicon wafers which are processed through a Photocluster cell to define a resist pattern for defect inspection. In order to monitor a large set of equipment and resist types, a large quantity of clean Silicon wafers are required. The reuse of these silicon photo monitor wafers becomes difficult due to particles left on wafers after resist clean. Thus, the cost of daily photo defect monitor for equipment/process control becomes considerable. In this paper, we will discuss reusable thermal oxide test wafers as an alternative solution to Si wafers for a cost effective photo defect monitor. The required oxide thickness for I-line and DUV resists was calculated from Prolith/2 simulation. By using a special clean with Sulfuric Acid/Hydrogen Peroxide mixture (SPM) and followed by an Ammonium Hydroxide/Hydrogen Peroxide mixture (APM) for resist strip, very low particle counts were achieved for oxide substrate and better than those of Silicon wafers. Furthermore, due to low oxide thickness loss per clean cycle (1 - 2 A), oxide test wafers retain the optical characteristics for defect metrology tools to work without any recalibration. This makes the oxide photo defect monitor process very robust and production worthy. KLA defect data on unpatterned and patterned oxide test wafers for 20 or more reworks, will be shown. They will be compared to control Silicon test wafers. Some issues with exposure and focus condition and their effect on KLA defect detection will be discussed. Finally, a simple cost analysis model will show the potential saving benefit of oxide test wafer.

Proceedings Article | 8 June 1998 Paper

Plasma etch process characterization: an application of atomic force microscopy

Wenge Yang, Bhanwar Singh

Proceedings Volume 3332, (1998) https://doi.org/10.1117/12.308745

KEYWORDS: Etching, Plasma etching, Metrology, Critical dimension metrology, Semiconducting wafers, Plasma, Atomic force microscopy, Metals, Scanning electron microscopy, Calibration

Read Abstract +

Proceedings Article | 8 June 1998 Paper

Toward a unified advanced CD-SEM specification for sub-0.18-um technology

John Allgair, Charles Archie, G. Banke, E. Hal Bogardus, Joseph Griffith, Herschel Marchman, Michael Postek, Lumdas Saraf, Jerry Schlesinger, Bhanwar Singh, Neal Sullivan, Lee Trimble, Andras Vladar, Arnold Yanof

Proceedings Volume 3332, (1998) https://doi.org/10.1117/12.308724

KEYWORDS: Semiconducting wafers, Metrology, Pattern recognition, Scanning electron microscopy, Contamination, Lithography, Calibration, Standards development, Wafer testing, Electron microscopes

Read Abstract +

Proceedings Article | 21 May 1996 Open Access

Sub-0.35-um critical dimension metrology using atomic force microscopy

Kathryn Guarini, Bhanwar Singh, William Arnold

Proceedings Volume 2725, (1996) https://doi.org/10.1117/12.240111

KEYWORDS: Calibration, Critical dimension metrology, Photoresist materials, Metrology, Atomic force microscopy, Semiconducting wafers, Scanning electron microscopy, Semiconductors, Silicon, Atomic force microscope

Read Abstract +

DOWNLOAD PAPER

Proceedings Article | 9 June 1995 Paper

Improved resist profiles and CD control through optimized thin dielectric stacks

Christopher Lyons, Mahesh Agrawal, Bhanwar Singh

Proceedings Volume 2438, (1995) https://doi.org/10.1117/12.210381

KEYWORDS: Picture Archiving and Communication System, Critical dimension metrology, Oxides, Semiconducting wafers, Etching, Diffusion, Interfaces, Scanning electron microscopy, Dielectrics, Silicon

Read Abstract +

Proceedings Article | 1 May 1994 Paper

0.35-micron DUV lithography for poly gate layer

Nigel Farrar, Bhanwar Singh

Proceedings Volume 2196, (1994) https://doi.org/10.1117/12.174135

KEYWORDS: Deep ultraviolet, Lithography, Photoresist processing, Bottom antireflective coatings, Optical lithography, Reflectivity, Line edge roughness

Read Abstract +

Proceedings Article | 4 August 1993 Paper

Integrated circuit wafer reflectivity measurement in the UV and DUV and its application for ARC characterization

Bhanwar Singh, Sesh Ramaswami, Warren Lin, Nagesh Avadhany

Proceedings Volume 1926, (1993) https://doi.org/10.1117/12.149012

KEYWORDS: Reflectivity, Tin, Semiconducting wafers, Deep ultraviolet, Aluminum, Silicon, Thin films, Photoresist materials, Coating, Ultraviolet radiation

Read Abstract +

Proceedings Article | 1 June 1992 Paper

Measurement of multilayer film and reflectivity on wafers using ultraviolet-visible microspectrophotometry

Warren Lin, Vincent Coates, Bhanwar Singh

Proceedings Volume 1673, (1992) https://doi.org/10.1117/12.59833

KEYWORDS: Oxides, Ultraviolet radiation, Reflectivity, Semiconducting wafers, Silicon, Multilayers, Visible radiation, Diffraction gratings, Sensors, Silica

Read Abstract +

Proceedings Article | 1 July 1991 Paper

Metrology issues associated with submicron linewidths

Khoi Phan, John Nistler, Bhanwar Singh

Proceedings Volume 1464, (1991) https://doi.org/10.1117/12.44455

KEYWORDS: Scanning electron microscopy, Calibration, Metrology, Integrated optics, Integrated circuits, Inspection, Process control, Critical dimension metrology, Optical testing, Photomasks

Read Abstract +

Proceedings Article | 1 July 1991 Open Access

Phase-shift mask technology: requirements for e-beam mask lithography

Steven Dunbrack, Andrew Muray, Charles Sauer, Richard Lozes, John Nistler, William Arnold, David Kyser, Anna Maria Minvielle, Moshe Preil, Bhanwar Singh, Michael Templeton

Proceedings Volume 1464, (1991) https://doi.org/10.1117/12.44444

KEYWORDS: Photomasks, Inspection, Reticles, Integrated circuits, Process control, Metrology, Electron beam lithography, Phase shifts, Overlay metrology, Photomicroscopy

Read Abstract +

DOWNLOAD PAPER

Proceedings Article | 1 July 1991 Paper

Semiwafer metrology project

Marylyn Bennett, William Hiatt, Laurie Lauchlan, Lynda Hannemann-Mantalas, Hans Rottmann, Mark Seliger, Bhanwar Singh, Don Yansen

Proceedings Volume 1464, (1991) https://doi.org/10.1117/12.44472

KEYWORDS: Metrology, Scanning electron microscopy, Semiconducting wafers, Calibration, Process control, Reticles, Integrated circuits, Inspection, Etching, Integrated optics

Read Abstract +

Proceedings Article | 1 June 1990 Open Access

0.5-um photolithography using high-numerical-aperture I-line wafer steppers

William Arnold, Anna Maria Minvielle, Khoi Phan, Bhanwar Singh, Michael Templeton

Proceedings Volume 1264, (1990) https://doi.org/10.1117/12.20184

KEYWORDS: Optical lithography, Semiconducting wafers, Lithography, Silicon, Chlorine, Monochromatic aberrations, Helium, Scanning electron microscopy, Printing, Deep ultraviolet

Read Abstract +

DOWNLOAD PAPER

Showing 5 of 34 publications

Proceedings Volume Editor (9)

SPIE Conference Volume | 10 September 2007

Advanced Characterization Techniques for Optics, Semiconductors, and Nanotechnologies III

SPIE Conference Volume | 18 August 2005

Advanced Characterization Techniques for Optics, Semiconductors, and Nanotechnologies II

SPIE Conference Volume | 4 November 2003

Advanced Characterization Techniques for Optics, Semiconductors, and Nanotechnologies

SPIE Conference Volume | 11 November 2002

Advanced Characterization Techniques for Optical, Semiconductor, and Data Storage Components

SPIE Conference Volume | 10 December 2001

Optical Metrology Roadmap for the Semiconductor, Optical, and Data Storage Industries II

Showing 5 of 9 publications

Conference Committee Involvement (23)

Metrology, Inspection, and Process Control for Microlithography XXII

25 February 2008 | San Jose, California, United States

Advanced Characterization Techniques for Optics, Semiconductors, and Nanotechnologies III

28 August 2007 | San Diego, California, United States

Metrology, Inspection, and Process Control for Microlithography XXI

26 February 2007 | San Jose, California, United States

Data Analysis and Modeling for Patterning Control III

23 February 2006 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XX

20 February 2006 | San Jose, California, United States

Advanced Characterization Techniques for Optics, Semiconductors, and Nanotechnologies II

2 August 2005 | San Diego, California, United States

Data Analysis and Modeling for Process Control II

3 March 2005 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XIX

28 February 2005 | San Jose, California, United States

Data Analysis and Modeling for Process Control

26 February 2004 | Santa Clara, California, United States

Metrology, Inspection, and Process Control for Microlithography XVIII

23 February 2004 | Santa Clara, California, United States

Advanced Characterization Techniques for Optics, Semiconductors, and Nanotechnologies

3 August 2003 | San Diego, California, United States

Advanced Microelectronic Manufacturing

27 February 2003 | Santa Clara, United States

Metrology, Inspection, and Process Control for Microlithography XVII

24 February 2003 | Santa Clara, California, United States

Advanced Characterization Techniques for Optical, Semiconductor, and Data Storage Components

10 July 2002 | Seattle, WA, United States

Design, Process Integration, and Characterization for Microelectronics

7 March 2002 | Santa Clara, United States

Optical Metrology Roadmap for the Semiconductor, Optical, and Data Storage Industries

2 August 2001 | San Diego, CA, United States

Bogus Conference -- Advisory Board and Organizing Committee

27 November 2000 | Singapore, Singapore

International Symposium on Microelectronics and Assembly

27 November 2000 | Singapore, Singapore

Challenges in Process Integration and Device Technology

18 September 2000 | Santa Clara, CA, United States

Optical Metrology Roadmap for the Semiconductor, Optical, and Data Storage Industries

30 July 2000 | San Diego, CA, United States

Lithography for Semiconductor Manufacturing

19 May 1999 | Edinburgh, United Kingdom

Metrology, Inspection, and Process Control for Microlithography XIII

15 March 1999 | Santa Clara, CA, United States

Metrology, Inspection, and Process Control for Microlithography XII

23 February 1998 | Santa Clara, CA, United States

Showing 5 of 23 Conference Committees

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years