The history of dummy fill in semiconductor design goes back many generations of technology
development. From its start with planarization requirements, fill needs have expanded across
many wafer process manufacturing steps. They include lithography, etch, deposition, surface
anneal, and device performance with stress analysis. Modern EDA tools have advanced to
automatically place dummy shapes to meet these new requirements. These include placing
multi-layer cell constructs, and multi-layer analysis during placement. New fill requirements
have affected downstream flows such as extraction and timing analysis, physical verification,
and RET flows. Further enhancements to fill tools and flows are under development to meet the
total DFM needs for the next generations of chips.
Device extraction and the quality of device extraction is becoming of increasing concern for integrated
circuit design flow. As circuits become more complicated with concomitant reductions in geometry, the
design engineer faces the ever burgeoning demand of accurate device extraction. For technology nodes of
65nm and below approximation of extracting the device geometry drawn in the design layout
polygons might not be sufficient to describe the actual electrical behavior for these devices, therefore
contours from lithographic simulations need to be considered for more accurate results.
Process window variations have a considerable effect on the shape of the device wafer contour, having an
accurate method to extract device parameters from wafer contours would still need to know which
lithographic condition to simulate. Many questions can be raised here like: Are contours that represent the
best lithography conditions just enough? Is there a need to consider also process variations? How do we
include them in the extraction algorithm?
In this paper we first present the method of extracting the devices from layout coupled with lithographic simulations. Afterwards a complete flow for circuit time/power analysis using lithographic contours is described. Comparisons between timing results from the conventional LVS method and Litho aware method are done to show the importance of litho contours considerations.