This paper takes static random-access-memory (SRAM)-based field-programmable-gate-array (FPGA) as the research object. Attention is focused on the configuration memory of this kind of FPGA, and the research has been devoted to the contents of the configuration memory and the configuration circuit to manage its contents. The single event upset (SEU) happening in the configuration memory doesn’t lead to a functional failure necessarily. The dynamic SEU is SEU which happens in the configuration memory and causes necessarily function failure. This paper introduces a test method of dynamic SUE rate for the SRAM-based FPGA by designing a FPGA with self-test function.
This paper describes how to design and develop an advanced Charge Coupled Device (CCD) timing generator which can obtain high precise CCD output signals. Above all, theory of the design and implementation of CCD timing generator is introduced based on Field Programmable Gate Array (FPGA) devices in detail. Secondly, it studies and analyzes the influencing factors that the waveform of CCD driving timing signals have on qualities of CCD output signals, which contain duty-cycle of HCCD clock, positive width of RST, signal-skew and delays among these signals. Then some skills are presented to improve and optimize the design in the phase of coding, compiling and placement and routing, which include code constraint, incremental placement and so on. Finally, simulation and verification of the design are performed with simulation tools, and hardware tests are carried out and experiment results are proved by oscilloscope.
This paper describes how placement and routing with manual intervention to improve the digital signal performance. According to studying and analyzing the features of Field Programmable Gate Array (FPGA) devices which include chip architecture and timing characteristics, a new approach is presented that some key logic modules can be relocated reasonably with manual intervention after completing successful place-and-route automatically. An example is given to illustrate this method. In this example, in order to improve remote sensing Charge Coupled Device (CCD) camera performance, signal-skew and delays among CCD driving timing signals must be controlled accurately and easily. This method can make CCD driving timing signals obtain the zero-skew which means tCO (clock to out) values for all these signals are equal, and finally hardware tests are carried out and experiment results are measured precisely by oscilloscope.
Proc. SPIE. 8897, Electro-Optical Remote Sensing, Photonic Technologies, and Applications VII; and Military Applications in Hyperspectral Imaging and High Spatial Resolution Sensing
KEYWORDS: Optical filters, Digital image processing, Image processing, Digital filtering, Remote sensing, Digital imaging, Signal processing, Image filtering, Modulation transfer functions, Electronic filtering
As the development of semiconductor technology, the manufacture process of CCD sensors has been improved continuously. In recent years some new technologies appear on CCD sensors. Analog pixel Binning technology is one of them. In this paper, a new signal-processing system of digital pixel binning based on bi-cubic filtering algorithm is designed .The system overcomes the shortcomings of losing some image details, caused by analog pixel binning which does simply summation of pixel signals. The signal-processing system of digital pixel binning can keep high frequency information through bi-cubic filtering algorithm, which can improve the contrast and MTF of the remote sensing images. This system can achieve pixel binning with lower computational complexity and also it has the good real-time capability for large-scale remote sensing images.