Increased data rates have motivated the investigation of advanced modulation schemes, such as four-level pulseamplitude modulation (PAM4), in optical interconnect systems in order to enable longer transmission distances and operation with reduced circuit bandwidth relative to non-return-to-zero (NRZ) modulation. Employing this modulation scheme in interconnect architectures based on high-Q silicon photonic microring resonator devices, which occupy small area and allow for inherent wavelength-division multiplexing (WDM), offers a promising solution to address the dramatic increase in datacenter and high-performance computing system I/O bandwidth demands. Two ring modulator device structures are proposed for PAM4 modulation, including a single phase shifter segment device driven with a multi-level PAM4 transmitter and a two-segment device driven by two simple NRZ (MSB/LSB) transmitters. Transmitter circuits which utilize segmented pulsed-cascode high swing output stages are presented for both device structures. Output stage segmentation is utilized in the single-segment device design for PAM4 voltage level control, while in the two-segment design it is used for both independent MSB/LSB voltage levels and impedance control for output eye skew compensation. The 65nm CMOS transmitters supply a 4.4V<sub>ppd</sub> output swing for 40Gb/s operation when driving depletion-mode microring modulators implemented in a 130nm SOI process, with the single- and two-segment designs achieving 3.04 and 4.38mW/Gb/s, respectively. A PAM4 optical receiver front-end is also described which employs a large input-stage feedback resistor transimpedance amplifier (TIA) cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity. Receiver linearity, critical in PAM4 systems, is achieved with a peak-detector-based automatic gain control (AGC) loop.
Directly modulated vertical-cavity surface-emitting lasers (VCSELs) are commonly used in short-reach optical interconnect applications. To enable efficient optical interconnect transceiver systems operating at data rates up to 25 Gb/s and beyond, cosimulation environments, which allow for the optimization of driver circuitry with accurate compact VCSEL models, are necessary. A comprehensive VCSEL model, which captures thermally dependent electrical and optical dynamics and provides direct current, small-, and large-signal simulation capabilities with self-consistency, is presented. The device’s electrical behavior is described with an equivalent circuit, which captures both large-signal operation and electrical parasitics, while the optical response is captured with a rate-equation-based model. Bias and temperature dependencies are incorporated into both key electrical and optical model parameters. Experimental verification of the model is performed at 25 Gb/s with a 990-nm VCSEL to study the impact of bias current level and substrate temperature.