The tight overlay budgets required for 45nm and beyond make overlay control a very important topic. With the adoption
of immersion lithography, the incremental complexity brings much more difficulty to analyzing the source of variation
and optimizing the sampling strategy. In this paper, there will be a discussion about how the use of an advanced
sampling methodology and strategy can help to overcome this overlay control problem and insure sufficient overlay
information to be captured for effective production lot excursion detection as well as rework decision making. There
will also be a demonstration of the different correction methodologies to improve overlay control for dual-stage systems
in order to maximize the productivity benef its with minimal impact to overlay performance.
As advanced semiconductor companies move forward to the 45nm technology node, traditional overlay sampling and
linear correction used in dry lithography become less feasible to bring overlay control into the desired budget. New
overlay control methodologies need to be established to meet the needs of much tighter overlay budgets in the
immersion lithography process. Overlay source of variance (SOV) was first investigated to understand the major
contributor of overlay error sources. The SOVis broken down into wafer, field, and random components in order to
utilize the SOV information to prioritize overlay improvement decisions. High order wafer level or field level error
components are commonly observed as a significant contributor and requires attention to bring the overlay residual into
the desired limit. Optimal sample is determined in considering sample plan robustness and throughput impact while
increasing sampling becomes a necessity in 45nm technology node.
According to the ITRS roadmap, low k1 imaging requires extremely tight control
of Critical Dimension (CD). Maintaining the same performance from one exposure to
another for new imaging requirements has become increasingly important, particularly
for matching dry and wet systems. Tool to tool CD matching depends on many factors,
for example, lens aberrations, partial coherence, laser spectral bandwidth and short range
We have performed a detailed study of laser bandwidth effects on tool CD matching for
typical 65nm node structures exposed on immersion ArF scanners. A high accuracy
on-board spectrometer was used to characterize the lithography
Laser bandwidth, allowing measurements of both the FWHM and E95 parameters of the
laser spectrum. Spectral bandwidth was adjusted over a larger range than normally
experienced during wafer exposures using Cymer's Tunable Advanced Bandwidth
Stabilization device (T-ABS) to provide controlled changes in bandwidth while
maintaining all other laser performance parameters within specification.
Measurements of both Lines and Contact Holes on 65nm node structures through all
pitches were made and correlated with bandwidth to determine the sensitivity of IDB and
C/H to bandwidth variation. We demonstrated that bandwidth can be adjusted for CD
matching on different tool using the T-ABS function.
As semiconductor process technology moves to smaller generations (65nm and beyond), the contact pattern printing
becomes the most difficult challenge in the lithography field. The reason comes from the smaller feature size and pitch of
contact/via pattern printing that is similar to 2D (two-dimensional) patterning. Contact and via patterns need better image
contrast than line/space patterns in pattern printing. Hence, contact/via printing needs a higher k1 value than others.
In 65nm generation experience, the k1 is ~0.44 on a 0.85 NA exposure tool. A larger NA exposure tool is expensive
and developed slower than the motivation of generation. Hence, the process is difficult to achieve by obtaining larger NA
exposure tools. The k1 requirement of 45nm (logic) contact pattering (minimum pitch: 140nm) is ~0.34 on a 0.93 NA
exposure tool that is available currently. RET (resolution enhancement technology) is necessary to achieve the difficult
process goal. Splitting pitch technology is an RET approach to solving 45nm contact pattering.
In this paper, we use a 2P1E (2 photo exposure and 1 etching) approach to meet our process requirements. The
original layout is split into dense pitch pattern and semi-iso to iso pattern parts by software. Utilizing strong OAI
(off-axis-illumination) on dense pattern part and weak OAI on semi-iso to iso pattern part can obtain better process