Dr. Bo Su Profile

Dr. Bo Su

Sr. Director of Product Management at D2S Inc

SPIE Involvement:

Editorial Board Member: Journal of Micro/Nanolithography, MEMS, and MOEMS | Editorial Board Member: Journal of Micro/Nanopatterning, Materials, and Metrology | Author

Publications (33)

SPIE Journal Paper | 6 February 2024

Make the impossible possible: use variable-shaped beam mask writers and curvilinear full-chip inverse lithography technology for 193i contacts/vias with mask-wafer co-optimization

Linyong (Leo) Pang, Sha Lu, Ezequiel Vidal Russell, Yang Lu, Michael Lee, Jennefir Digaum, Ming-Chuan Yang, P. Jeffrey Ungar, Michael Pomerantsev, Mariusz Niewczas, Kechang Wang, Bo Su, Michael Meyer, Aki Fujimura

JM3, Vol. 23, Issue 01, 011207, (February 2024) https://doi.org/10.1117/12.10.1117/1.JMM.23.1.011207

KEYWORDS: Vestigial sideband modulation, Semiconducting wafers, Optical proximity correction, SRAF, Critical dimension metrology, Lithography, Printing, Design, Scanning electron microscopy, Photomask technology

Read Abstract +

SPIE Journal Paper | 17 November 2021 Open Access

Open Access

Breakthrough curvilinear ILT enabled by multi-beam mask writing

Linyong Pang, Ezequiel Vidal-Russell, Bill Baggenstoss, Michael Lee, Jennefir Digaum, Ming-Chuan Yang, P. Jeffrey Ungar, Ali Bouaricha, Kechang Wang, Bo Su, Ryan Pearman, Aki Fujimura

JM3, Vol. 20, Issue 04, 041405, (November 2021) https://doi.org/10.1117/12.10.1117/1.JMM.20.4.041405

KEYWORDS: Photomasks, Semiconducting wafers, Optical proximity correction, Lithography, Vestigial sideband modulation, Semiconductor manufacturing, Manufacturing, Extreme ultraviolet, Physics, Semiconductors

Read Abstract +

Background: Multi-beam mask writers have been one of the most significant additions to the semiconductor manufacturing equipment arsenal in over a decade. The ability of multi-beam mask writers to write masks with a constant write time regardless of mask shapes or complexity has made them an eagerly anticipated advancement to help write curvilinear mask shapes for both today’s advanced 193i nodes and for extreme ultra-violet (EUV) lithography in the future. Perhaps the most obvious application for these new pixel-based mask writers is the production of curvilinear inverse lithography technology (ILT) masks. ILT has been seen as a promising solution to many of the challenges of advanced-node lithography, whether optical or EUV. However, the runtimes and mask writing times associated with this computational technique have limited its practical application. Until recently, it had been used for critical “hotspots” on chips, but had not been used for entire chips. Aim: The introduction of multi-beam mask writing, along with the advent of graphics processing unit (GPU)-accelerated computing for mask and wafer, have enabled the introduction of a new approach to full-chip ILT using these new technologies. The goal was to produce full-chip, curvilinear ILT within the traditional turnaround times of mask shops. Approach: The solution to the runtime problem for ILT has been particularly vexing, as the traditional approach to runtime improvement—partitioning and stitching—has failed to produce satisfactory results, either in terms of runtime or in terms of quality. In 2019, D2S introduced an entirely new, stitchless approach, systematically designed for ILT, multi-beam mask writers, and GPU acceleration, that makes full-chip ILT a practical reality in production for the first time. Results: We present this new ILT approach, first introduced using a multi-beam mask writer to create the complex curvilinear mask shapes. We also review findings that targeting curvilinear mask shapes creates masks that are more resilient to manufacturing variation. Finally, we review the results of this new, stitchless full-chip curvilinear ILT as applied to memory chip making. We show mask making and wafer print results, including pattern fidelity and process window, to demonstrate the actual benefit of such technologies—a doubling in the wafer process window—for semiconductor manufacturing.

Proceedings Article | 7 October 2020 Presentation + Paper

Presentation + Paper

Enabling faster VSB writing of 193i curvilinear ILT masks that improve wafer process windows for advanced memory applications

Linyong (Leo) Pang, Ezequiel Russell, Bill Baggenstoss, Yang Lu, Michael Lee, Jennefir Digaum, Ming-Chuan Yang, Ryan Pearman, P. Jeffrey Ungar, Lu Sha, Ali Bouaricha, Michael Pomerantsev, Mariusz Niewczas, Kechang Wang, Bo Su, Michael Meyer, Aki Fujimura

Proceedings Volume 11518, 115180W (2020) https://doi.org/10.1117/12.2579729

Read Abstract +

Proceedings Article | 31 March 2020 Presentation + Paper

Presentation + Paper

TrueMask ILT MWCO: full-chip curvilinear ILT in a day and full mask multi-beam and VSB writing in 12 hrs for 193i

Linyong (Leo) Pang, P. Jeffrey Ungar, Ali Bouaricha , Lu Sha, Michael Pomerantsev, Mariusz Niewczas, Kechang Wang, Bo Su, Ryan Pearman, Aki Fujimura

Proceedings Volume 11327, 113270K (2020) https://doi.org/10.1117/12.2554867

KEYWORDS: Photomasks, Semiconducting wafers, SRAF, Lithography, Optical proximity correction, Extreme ultraviolet, Critical dimension metrology, Mask making

Read Abstract +

Proceedings Article | 3 October 2019 Paper

Paper

Study of mask and wafer co-design that utilizes a new extreme SIMD approach to computing in memory manufacturing: full-chip curvilinear ILT in a day

Linyong Pang, Ezequiel Vidal Russell, Bill Baggenstoss, Michael Lee, Jennefir Digaum, Ming-Chuan Yang, P. Jeffrey Ungar, Ali Bouaricha, Kechang Wang, Bo Su, Ryan Pearman, Aki Fujimura

Proceedings Volume 11148, 111480U (2019) https://doi.org/10.1117/12.2534629

KEYWORDS: Photomasks, Semiconducting wafers, Optical proximity correction, Lithography, Manufacturing, Vestigial sideband modulation, Semiconductor manufacturing, Extreme ultraviolet, Physics, Semiconductors, Semiconducting wafers, Optical proximity correction, Lithography, Manufacturing, Vestigial sideband modulation, Semiconductor manufacturing, Extreme ultraviolet, Physics, Semiconductors

Read Abstract +

In advanced semiconductor memory manufacturing, mask and lithography are critical for patterning. In this paper we jointly study the benefits of a mask and wafer co-design that utilizes a new extreme single instruction multiple data (SIMD) approach to computing. Wafer results will be shown demonstrating the benefits of the approach. Unlike traditional EDA software that runs on customers’ computer farm, this new approach leverages and maximizes GPU acceleration. In this study, software speed and quality, mask writing strategy, wafer pattern fidelity and process window are examined and analyzed. Inverse lithography technology (ILT) has been seen as a promising solution to many of the challenges of advanced-node lithography, whether optical or EUV. However, the runtimes associated with this computational technique have limited its practical application. Until now, it has been used for critical “hotspots” on chips, but has not been used for entire chips. The solution to the runtime problem for ILT has been particularly vexing, as the traditional approach to runtime improvement – partitioning and stitching – has failed to produce satisfactory results, either in terms of runtime or in terms of quality. D2S has adopted an entirely new, stitchless approach, creating a holistically conceived, purpose-built system for ILT, This system includes a unique GPU-accelerated approach that emulates a single, giant GPU/CPU pair that can compute an entire full-chip ILT solution at once. This novel approach, systematically designed for ILT and GPU acceleration, makes full-chip ILT a practical reality in production for the first time. For the most advanced DRAM manufacturing using 193nm immersion lithography, every aspect of design, mask, and lithography, including quality of the process, accuracy, and turn-around-time, need to be optimized. Any new technique that significantly improve one or more elements of such complete process are welcome. Recently a number of new technologies, such as multi-beam mask writer, GPU accelerated computing for mask and wafer, are emerged and are reshaping the mask and lithography. This new stitchless full chip curvilinear ILT is applied to memory chip making. We will show mask making and wafer print results, including pattern fidelity and process window, to show the actual benefits of such technologies for semiconductor manufacturing.

Proceedings Article | 31 October 2017 Presentation + Paper

Presentation + Paper

Full-chip GPU-accelerated curvilinear EUV dose and shape correction

Ryan Pearman, Abhishek Shendre, Oleg Syrel, Harold Zable, Ali Bouaricha , Mariusz Niewczas , Bo Su , Leo Pang , Aki Fujimura

Proceedings Volume 10451, 1045108 (2017) https://doi.org/10.1117/12.2281686

KEYWORDS: Extreme ultraviolet, Photomasks, Data modeling, Vestigial sideband modulation, Point spread functions, Extreme ultraviolet lithography, Raster graphics, Scattering, Electro optical modeling, Process modeling

Read Abstract +

Proceedings Article | 13 July 2017 Paper

Paper

Model-based MPC enables curvilinear ILT using either VSB or multi-beam mask writers

Linyong Pang, Yutetsu Takatsukasa, Daisuke Hara, Michael Pomerantsev, Bo Su, Aki Fujimura

Proceedings Volume 10454, 1045407 (2017) https://doi.org/10.1117/12.2281110

KEYWORDS: Photomasks, Model-based design, Lithography, Computational lithography, Mask making, Process modeling, Optical proximity correction, Etching, Modulation, Convolution, Image processing

Read Abstract +

Proceedings Article | 13 July 2017 Paper

Paper

Simulation-based MDP verification for leading-edge masks

Bo Su, Oleg Syrel, Michael Pomerantsev, Kazuyuki Hagiwara, Ryan Pearman, Leo Pang, Aki Fujimara

Proceedings Volume 10454, 1045409 (2017) https://doi.org/10.1117/12.2280841

KEYWORDS: Photomasks, Computer simulations, Process modeling, Model-based design, Data modeling, Optical proximity correction, Electron beam lithography, Reactive ion etching, Computer aided design, Mask making

Read Abstract +

For IC design starts below the 20nm technology node, the assist features on photomasks shrink well below 60nm and the printed patterns of those features on masks written by VSB eBeam writers start to show a large deviation from the mask designs. Traditional geometry-based fracturing starts to show large errors for those small features. As a result, other mask data preparation (MDP) methods have become available and adopted, such as rule-based Mask Process Correction (MPC), model-based MPC and eventually model-based MDP.

The new MDP methods may place shot edges slightly differently from target to compensate for mask process effects, so that the final patterns on a mask are much closer to the design (which can be viewed as the ideal mask), especially for those assist features. Such an alteration generally produces better masks that are closer to the intended mask design. Traditional XOR-based MDP verification cannot detect problems caused by eBeam effects. Much like model-based OPC verification which became a necessity for OPC a decade ago, we see the same trend in MDP today.

Simulation-based MDP verification solution requires a GPU-accelerated computational geometry engine with simulation capabilities. To have a meaningful simulation-based mask check, a good mask process model is needed. The TrueModel® system is a field tested physical mask model developed by D2S. The GPU-accelerated D2S Computational Design Platform (CDP) is used to run simulation-based mask check, as well as model-based MDP. In addition to simulation-based checks such as mask EPE or dose margin, geometry-based rules are also available to detect quality issues such as slivers or CD splits. Dose margin related hotspots can also be detected by setting a correct detection threshold.

In this paper, we will demonstrate GPU-acceleration for geometry processing, and give examples of mask check results and performance data. GPU-acceleration is necessary to make simulation-based mask MDP verification acceptable.

SPIE Press Book | 25 September 2015

Introduction to Metrology Applications in IC Manufacturing

Eric Solecky, Alok Vaid, Bo Su

KEYWORDS: Metrology, Semiconducting wafers, Overlay metrology, Manufacturing, Photomasks, Inspection, Process control, Critical dimension metrology, Calibration, Semiconductors

Read Description +

Introduction to Metrology Applications in IC Manufacturing

Proceedings Article | 8 October 2014 Paper

Paper

Trends in mask data preparation

Aki Fujimura, Liyong Pang, Bo Su, Yohan Choi

Proceedings Volume 9235, 923508 (2014) https://doi.org/10.1117/12.2073368

KEYWORDS: Photomasks, Monte Carlo methods, Manufacturing, Critical dimension metrology, Optical proximity correction, Modulation, Vestigial sideband modulation, Backscatter, Convolution, Electrons

Read Abstract +

Proceedings Article | 28 June 2013 Paper

Paper

In-situ repair qualification by applying Computational Metrology and Inspection (CMI) technologies

C. Y. Chen, Ivan Wei, Laurent Tuo, C. S. Yoo, Dongxue Chen, Danping Peng, Masaki Satake, Bo Su, Linyong Pang

Proceedings Volume 8701, 870108 (2013) https://doi.org/10.1117/12.2030688

KEYWORDS: Photomasks, Scanning electron microscopy, Inspection, Image processing, Metrology, Image analysis, Scanners, Etching, Time metrology, Error analysis

Read Abstract +

Proceedings Article | 15 March 2012 Paper

Paper

Yield impacting systematic defects search and management

Jing Zhang, Qingxiu Xu, Xin Zhang, Xing Zhao, Jay Ning, Guojie Cheng, Shijie Chen, Gary Zhang, Abhishek Vikram, Bo Su

Proceedings Volume 8327, 832716 (2012) https://doi.org/10.1117/12.918068

KEYWORDS: Semiconducting wafers, Wafer inspection, Metals, Inspection, Scanning electron microscopy, Defect detection, Image processing, Bridges, Semiconductors, Image classification

Read Abstract +

Despite great effort before design tapeout, there are still some pattern related systematic defects showing up in production, which impact product yield. Through various check points in the production life cycle endeavor is made to detect these defective patterns. It is seen that apart from the known defective patterns, slight variations of polygon sizes and shapes in the known defective patterns also cause yield loss. This complexity is further compounded when interactions among multiple process layers causes the defect. Normally the exact pattern matching techniques cannot detect these variations of the defective patterns. With the currently existing tools in the fab it is a challenge to define the 'sensitive patterns', which are arbitrary variations in the known 'defective patterns'. A design based approach has been successfully experimented on product wafers to detect yield impacting defects that greatly reduces the TAT for hotspot analysis and also provides optimized care area definition to enable high sensitivity wafer inspection. A novel Rule based pattern search technique developed by Anchor Semiconductor has been used to find sensitive patterns in the full chip design. This technique allows GUI based pattern search rule generation like, edge move or edge-to-edge distance range, so that any variations of a particular sensitive pattern can be captured and flagged. Especially the pattern rules involving multiple process layers, like M1-V1-M2, can be defined easily using this technique. Apart from using this novel pattern search technique, design signatures are also extracted around the defect locations in the wafer and used in defect classification. This enhanced defect classification greatly helps in determining most critical defects among the total defect population. The effectiveness of this technique has been established through design to defect correlation and SEM verification. In this paper we will report details of the design based experiments that were successfully run on multiple process layers in production device.

Proceedings Article | 14 October 2011 Paper

Paper

Simulation based mask defect printability verification and disposition. Part II

Eric Guo, Irene Shi, Blade Gao, Nancy Fan, Guojie Cheng, Li Ling, Ke Zhou, Gary Zhang, Ye Chen, Chingyun Hsiang, Bo Su

Proceedings Volume 8166, 81662D (2011) https://doi.org/10.1117/12.896879

KEYWORDS: Photomasks, Scanning electron microscopy, Image processing, Wafer-level optics, Semiconducting wafers, Lithography, Inspection, Process modeling, Optical inspection, Software development

Read Abstract +

We have reported the first part of the work in 2009 BACUS meeting [1], using primarily SEM mask defect images as input. This paper is the extension of that work using mask optical inspection images with a new image process algorithm. Simulation has been widely used in overall lithography process, called computational lithography, as an effective way for cost and time reduction. As the industry moves towards 45nm and 32nm technology nodes in production, the mask inspection, with increased sensitivity and shrinking critical defect size, catches more and more nuisance and false defects. Increased defect counts pose great challenges in the post inspection defect classification and disposition: which defects are real defects, and among the real defects, which defects should be repaired and how to verify the post-repair defects. In this paper, we report simulation mask defect printability check and disposition results extending beyond SEM mask defect images [1] into optical inspection mask defects images to demonstrate cost and time reduction by simulation in mask defect management area. A new algorithm has been developed in the software tool to convert optical inspection mask defect images into "pseudo-defect" polygons in GDS format. Then, the converted defect polygons were filled with the correct tone to form mask patterns and were merged back into the original design GDS. With lithography process model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be simulated. If such complicated model is not available, a simple optical model can be used to get aerial image intensity of AOI. With build-in contour analysis functions, the software can easily compare the contour (or intensity) differences between real mask (with defect) and normal mask (without defect). With user provided judging criteria, software can be easily disposition the defect based on contour comparison. The software has been tested and adapted for production use. We will present some accuracy test results against AIMS tool or wafer CDs in defect printability check.

Proceedings Article | 3 April 2010 Paper

Paper

Detection of OPC conflict edges through MEEF analysis

Li-Fu Chang, Chang-Il Choi, Guojie Cheng, Abhishek Vikram, Gary Zhang, Bo Su

Proceedings Volume 7641, 764111 (2010) https://doi.org/10.1117/12.846673

KEYWORDS: Optical proximity correction, Design for manufacturing, Design for manufacturability, Lithography, Manufacturing, Edge detection, Semiconductors, Photomasks, Critical dimension metrology, Mask making

Read Abstract +

Semiconductor foundries at 65nm, 45nm, and more advanced technologies have witnessed high-yield mass production to be intimately correlated to the practice of adaptive DFM (Design for Manufacturability). With device performance variance easily exceeding 50% for 65nm and below, adaptive actions by designers, such as modifying layouts to relieve potential DFM risks, is found to be a very efficient approach to high yield manufacturing. Rigorous MEEF estimation based methods have been proposed to achieve adaptive DFM by predicting mask writing variations at early stages (cell/block levels) of designs. In a recent study, we discovered that by adding MEEF check in simulation contour based OPC verification flow, and by comparing MEEF changes of pre and post OPC hotspots, it is possible to separate OPC issues from design issues, in particular, for hotspot patterns with tight spaces with little room for any biases. We found that hotspot patterns with tight spaces usually create OPC conflict edges-correcting one edge will result in increasing MEEF at other edge, or vice versa. While advancement in OPC technology continues to improve MEEF performance, nevertheless OPC-conflicting edges almost always exist in designs at 65nm and below. In this paper, we first demonstrate the existence of OPC conflict edge hotspots using MEEF analysis. In particular, the increase of MEEF after OPC on those edges indicates that they have smaller process window than pre-OPC ones. In certain cases, design modification is necessary to correct such OPC conflicting edges. Based on the finding, we propose a practical methodology of detecting design related OPC edge conflicting hotspots in a pattern centric software-based DFM (design for manufacturability) flow. The methodology is aiming to detect patterns containing such conflicting edges, and pursuing layout actions on the design side to eliminate this issue. We will validate the flow using a real design case. In addition, the OPC edge conflicting hotspots can be clipped and saved in a designated pattern library as hotspot templates, and incoming designs can be quickly screened using exact and similar pattern search with those saved templates in the library.

Proceedings Article | 23 September 2009 Paper

Paper

Simulation based mask defect repair verification and disposition

Eric Guo, Shirley Zhao, Skin Zhang, Sandy Qian, Guojie Cheng, Abhishek Vikram, Ling Li, Ye Chen, Chingyun Hsiang, Gary Zhang, Bo Su

Proceedings Volume 7488, 74880G (2009) https://doi.org/10.1117/12.829692

KEYWORDS: Photomasks, Scanning electron microscopy, Semiconducting wafers, Image processing, Lithography, Process modeling, Optical proximity correction, Printing, Wafer-level optics, Inspection

Read Abstract +

As the industry moves towards sub-65nm technology nodes, the mask inspection, with increased sensitivity and shrinking critical defect size, catches more and more nuisance and false defects. Increased defect counts pose great challenges in the post inspection defect classification and disposition: which defect is real defect, and among the real defects, which defect should be repaired and how to verify the post-repair defects. In this paper, we address the challenges in mask defect verification and disposition, in particular, in post repair defect verification by an efficient methodology, using SEM mask defect images, and optical inspection mask defects images (only for verification of phase and transmission related defects). We will demonstrate the flow using programmed mask defects in sub-65nm technology node design. In total 20 types of defects were designed including defects found in typical real circuit environments with 30 different sizes designed for each type. The SEM image was taken for each programmed defect after the test mask was made. Selected defects were repaired and SEM images from the test mask were taken again. Wafers were printed with the test mask before and after repair as defect printability references. A software tool SMDD-Simulation based Mask Defect Disposition-has been used in this study. The software is used to extract edges from the mask SEM images and convert them into polygons to save in GDSII format. Then, the converted polygons from the SEM images were filled with the correct tone to form mask patterns and were merged back into the original GDSII design file. This merge is for the purpose of contour simulation-since normally the SEM images cover only small area (~1 μm) and accurate simulation requires including larger area of optical proximity effect. With lithography process model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be simulated. If such complicated model is not available, a simple optical model can be used to get simulated aerial image intensity in the AOI. With built-in contour analysis functions, the SMDD software can easily compare the contour (or intensity) differences between defect pattern and normal pattern. With user provided judging criteria, this software can be easily disposition the defect based on contour comparison. In addition, process sensitivity properties, like MEEF and NILS, can be readily obtained in the AOI with a lithography model, which will make mask defect disposition criteria more intelligent.

Proceedings Article | 17 October 2008 Paper

Paper

Combination of rule and pattern based lithography unfriendly pattern detection in OPC flow

Jae-Hyun Kang, Jae-Young Choi, Yeon-Ah Shim, Hye-Sung Lee, Bo Su, Walter Chan, Ping Zhang, Joanne Wu, Keun-Young Kim

Proceedings Volume 7122, 71221N (2008) https://doi.org/10.1117/12.801312

KEYWORDS: Optical proximity correction, Design for manufacturing, Lithography, Scanning electron microscopy, Detection and tracking algorithms, Databases, Bridges, Model-based design, Fuzzy logic, Defect detection

Read Abstract +

Foundry companies encounter again and again the same or similar lithography unfriendly patterns (Hot-spots) in different designs within the same technology node and across different technology nodes, which eluded design rule check (DRC), but detected again and again in OPC verification step. Since Model-based OPC tool applies OPC on whole-chip design basis, individual hot-spot patterns are treated same as the rest of design patterns, regardless of its severity. We have developed a methodology to detect those frequently appeared hot-spots in pre-OPC design, as well as post OPC designs to separate them from the rest of designs, which provide the opportunity to treat them differently in early OPC flow. The methodology utilizes the combination of rule based and pattern based detection algorithms. Some hotspot patterns can be detected using rule-based algorithm, which offer the flexibility of detecting similar patterns within pre-defined ranges. However, not all patterns can be detected (or defined) by rules. Thus, a pattern-based approach is developed using defect pattern library concept. The GDS/OASIS format hot-spot patterns can be saved into a defect pattern library. Fast pattern matching algorithm is used to detect hot-spot patterns in a design using the library as a pattern template database. Even though the pattern matching approach lacks the flexibility to detect patterns' similarity, but it has the capability to detect any patterns as long as a template exists. The pattern-matching algorithm can be either exact match or a fuzzy match. The rule based and pattern based hot-spot pattern detection algorithms complement each other and offer both speed and flexibility in hot spot pattern detection in pre-OPC and post-OPC designs. In this paper, we will demonstrate the methodology in our OPC flow and the benefits of such methodology application in production environment for 90nm designs. After the hot spot pattern detection, examples of special treatment to selected hot spot patterns will be shown.

Proceedings Article | 17 October 2008 Paper

Paper

Design for manufacturability guideline development: integrated foundry approach

Hyesung Lee, Yeon-Ah Shim, Jae-Young Choi, Kwang-Seon Choi, Joanne Wu, Bo Su, Xinwei Zhou, Kenny Kim

Proceedings Volume 7122, 712221 (2008) https://doi.org/10.1117/12.801421

KEYWORDS: Optical proximity correction, Design for manufacturing, Nanoimprint lithography, Design for manufacturability, Semiconducting wafers, Lithography, Silicon, Wafer manufacturing, Yield improvement, Manufacturing

Read Abstract +

Proceedings Article | 1 April 2008 Paper

Paper

Improvement on OPC completeness through pre-OPC hot spot detection and fix

Yeonah Shim, Jaeyoung Choi, Jeahee Kim, Bo Su, Ping Zhang, Keun-Young Kim

Proceedings Volume 6925, 692513 (2008) https://doi.org/10.1117/12.772409

KEYWORDS: Optical proximity correction, Design for manufacturing, Lithography, Semiconducting wafers, Data processing, Semiconductors, Failure analysis, Integrated circuit design, Design for manufacturability, Manufacturing

Read Abstract +

Proceedings Article | 1 April 2008 Paper

Paper

Pattern centric OPC flow: a special RET flow with fast turn-around-time

Tom Wang, Joanne Wu, Qingwei Liu, Gary Zhang, Benny Wang, Bo Su, Guojie Cheng

Proceedings Volume 6924, 69243V (2008) https://doi.org/10.1117/12.771617

KEYWORDS: Optical proximity correction, Model-based design, Resolution enhancement technologies, Optical lithography, Process modeling, Design for manufacturing, Performance modeling, Photomasks, Databases, Environmental sensing

Read Abstract +

Proceedings Article | 20 October 2006 Paper

Paper

Polysilicon gate and polysilicon wire CD/EPE defect detection and classification through process window

Scott Andrews, William Volk, Bo Su, Hong Du, Bhavaniprasad Kumar, Ramanamurthy Pulusuri, Abhishek Vikram, Xiaochun Li, Shaoyun Chen

Proceedings Volume 6349, 634932 (2006) https://doi.org/10.1117/12.694269

KEYWORDS: Inspection, Sensors, Critical dimension metrology, Optical proximity correction, Databases, Lithography, Resolution enhancement technologies, Photomasks, Defect detection, Target detection

Read Abstract +

Proceedings Article | 20 May 2006 Paper

Paper

Lithography process window enhancement using integrated design defect detection and fix

Bo Su, Melody Ma, Abhishek Vikram, William Volk, Hong Du, Gaurav Verma, Richard Morse, Chih-wei Chu, Becky Tsao, Char Lin, Jacky Chou, Sidney Tsai

Proceedings Volume 6283, 62830Q (2006) https://doi.org/10.1117/12.681851

KEYWORDS: Optical proximity correction, Inspection, Databases, Data modeling, Defect detection, Semiconducting wafers, Lithography, Scanning electron microscopy, Reticles, Process modeling

Read Abstract +

Proceedings Article | 9 November 2005 Paper

Paper

Inspection of integrated circuit database through reticle and wafer simulation: the lithography process window performance monitoring

Bo Su, Gaurav Verma, William Volk, Mohsen Ahmadian, Hong Du, Abhishek Vikram, Scott Andrews, Yung Feng Cheng, Yueh Lin Chou, Chuen Huei Yang, ChinLung Lin

Proceedings Volume 5992, 599244 (2005) https://doi.org/10.1117/12.633010

KEYWORDS: Inspection, Databases, Semiconducting wafers, Reticles, Scanning electron microscopy, Optical proximity correction, Calibration, Defect detection, Bridges, Data modeling

Read Abstract +

Proceedings Article | 7 November 2005 Paper

Paper

Applying reconfigurable RET across process window to create more robust manufacturing designs

Mark Laurance, Abhishek Vikram, Melody Ma, William Volk, Melissa Anderson, Scott Andrews, Bo Su, Hong Du, Gaurav Verma

Proceedings Volume 5992, 59921X (2005) https://doi.org/10.1117/12.631877

KEYWORDS: Optical proximity correction, Inspection, Resolution enhancement technologies, Manufacturing, Design for manufacturability, Model-based design, Photomasks, Lithography, Defect inspection, Semiconducting wafers

Read Abstract +

Proceedings Article | 22 August 2001 Paper

Paper

193-nm photoresist shrinkage after electron-beam exposure

Bo Su, Guy Eytan, Andrew Romano

Proceedings Volume 4344, (2001) https://doi.org/10.1117/12.436796

KEYWORDS: Scanning electron microscopy, Electron beams, Lithography, 3D metrology, Line edge roughness, Polymers, 3D image processing, Imaging technologies, Semiconducting wafers, Photoresist materials

Read Abstract +

Proceedings Article | 20 April 2001 Paper

Paper

Final CD control through slope/sidewall angle correlation with stepper defocus and electrical parametric

Robert Campbell, Bo Su, Terry Seregely, Steve Wallace, Frances Schantz

Proceedings Volume 4405, (2001) https://doi.org/10.1117/12.425243

KEYWORDS: Critical dimension metrology, Etching, Semiconducting wafers, Lithography, Process control, Control systems, Reactive ion etching, 3D metrology, Time metrology, Matrices

Read Abstract +

Proceedings Article | 18 August 2000 Paper

Paper

Automated OPC optimization using in-line CD-SEM

Bo Su, Mina Menaker, Nadav Haas, Ramkumar Subramanian, Bhanwar Singh

Proceedings Volume 4181, (2000) https://doi.org/10.1117/12.395714

KEYWORDS: Optical proximity correction, Photomasks, Semiconducting wafers, Wafer testing, Resolution enhancement technologies, Optical lithography, Printing, Lithography, Scanning electron microscopy, Optimization (mathematics)

Read Abstract +

Proceedings Article | 2 June 2000 Paper

Paper

Shape control using sidewall imaging

Bo Su, Ramiel Oshana, Mina Menaker, Yogev Barak, Xuelong Shi

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386476

KEYWORDS: Critical dimension metrology, Process control, Optical lithography, Resolution enhancement technologies, Scanners, Semiconducting wafers, Imaging systems, Etching, Electronic imaging, Lithography

Read Abstract +

Proceedings Article | 2 June 2000 Paper

Paper

Charging control through extraction field

Bo Su, Opher Harel

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386455

KEYWORDS: Scanning electron microscopy, Electron beams, Semiconducting wafers, Silicon, Metrology, Critical dimension metrology, Process control, Time metrology, Oxides, Signal processing

Read Abstract +

Proceedings Article | 26 July 1999 Paper

Paper

Design of 200-nm, 170-nm, and 140-nm DUV contact sweeper high-transmission attenuating phase-shift mask: II. Experimental results

Robert Socha, Xuelong Shi, Ken Holman, Mircea Dusa, Will Conley, John Petersen, J. Fung Chen, Thomas Laidig, Kurt Wampler, Roger Caldwell, M. Chu, Chung Jen Su, Kuei-Chun Hung, C. Chen, F. Wang, C. Le, Christophe Pierrat, Bo Su

Proceedings Volume 3679, (1999) https://doi.org/10.1117/12.354355

KEYWORDS: Reticles, Photomasks, Phase shifts, Printing, Transmittance, Lithography, Bessel functions, Deep ultraviolet, Chromium, Quartz

Read Abstract +

Proceedings Article | 11 June 1999 Paper

Paper

Experimental study of line-end shortening

Xuelong Shi, Robert Socha, Joseph Bendik, Mircea Dusa, Will Conley, Bo Su

Proceedings Volume 3678, (1999) https://doi.org/10.1117/12.350266

KEYWORDS: Diffusion, Optical proximity correction, Optical lithography, Chromium, Chemically amplified resists, Reticles, Deep ultraviolet, Scanning electron microscopy, Diffraction, Chemical reactions

Read Abstract +

Proceedings Article | 8 June 1998 Paper

Paper

Limitation of CD AFM on resist foot detection

Bo Su, K. Rajkumar, Mahesh Agrawal

Proceedings Volume 3332, (1998) https://doi.org/10.1117/12.308763

KEYWORDS: Calibration, Critical dimension metrology, Atomic force microscopy, Scanning electron microscopy, Semiconducting wafers, Silicon, 3D scanning, Metals, Contamination, Switching

Read Abstract +

Proceedings Article | 7 July 1997 Paper

Paper

Photolithographic lens characterization of critical dimension variation using empirical focal-plane modeling

Mircea Dusa, Bo Su, Stephen Dellarochetta, Terrence Zavecz

Proceedings Volume 3051, (1997) https://doi.org/10.1117/12.275989

KEYWORDS: Critical dimension metrology, Calibration, Monochromatic aberrations, Scanning electron microscopy, Electron microscopes, Diffraction

Read Abstract +

Exposure tool optimization in process development today extends beyond the classic concepts of exposure and focus setting. The lithographer must understand and tune the system for critical feature performance using variables such as Numerical Aperture (NA), Partial Coherence (PC), and critical level tool matching. In a previous study, the authors demonstrated that the phase-shift focal plane monitor (PSFM) accurately measures focal plane variations when appropriate calibrations are employed. That paper also described the development of a model for classic aberrations such as Astigmatism, Field Curvature and Coma. The model considered geometrical aberrations (Seidel) with radial symmetry across image plane as being the primary contributor to CD variation across stepper image plane. The publication correlated image plane focal results to an approximation of the stepper's Critical Dimension (CD) behavior for a matrix of NA and PC settings. In this study, we continue the analysis of the focus budget and CD uniformity using two generations of optical steppers in a 0.35 micrometers process. The analysis first addresses questions involving the use of the PSFM including the variation of calibration across the exposure field and the advantages of using field center or full field calibrations. We describe a method of easily measuring the uniformity of NA and PC across the exposure field. These new tools are then applied as an aid in lens image field characterization and tool-to-tool matching. The information gathered is then applied to measure image aberrations and predict CD variation across the image under various conditions of focus. The predictions are validated by a comparison against CD uniformity as measured by a commercial Scanning Electron Microscope. Present work confirmed previous work and recent assumptions that Zernike diffraction theory of aberration is most appropriate for current stepper lenses with local image plane focal variations across entire field being the major contributor to field CD variations.

Proceedings Article | 7 June 1996 Paper

Paper

Comprehensive focus-overlay-CD correlation to identify photolithographic performance

Mircea Dusa, Stephen Dellarochetta, Allen Fung, Bo Su, Terrence Zavecz

Proceedings Volume 2726, (1996) https://doi.org/10.1117/12.240922

KEYWORDS: Monochromatic aberrations, Data modeling, Distortion, Critical dimension metrology, Calibration, Scanning electron microscopy, Semiconducting wafers, Error analysis, Overlay metrology, Wavefronts

Read Abstract +

Showing 5 of 33 publications

SIGN IN TO:

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Advertisement

Advertisement