As the leading edge semiconductor technology development, the gate critical dimension (CD) shrinks below
90nm. The microlithography capability is limited by the exposure utility. The development of scanner is
focusing on low k that is implying that the high NA scanner is the main stream in the future. In addition, the
high NA reticle requirement is stricter than previous one. In aspect of mask manufacturing, reducing mask
topography effect is one of the various solutions, which is like lower mask blank flatness, should be lower than
1T flatness type or else. Unless the mask flatness, the absorber profile also could be a considerate effect element,
which is local topography effect contribution in wafer print window.
The main purpose of this study is verifying how much wafer prints window discrepancy between different
absorber profiles. The experiment pattern is designed for five kind of MoSi sidewall angle (SWA) on the same
mask, which could simultaneously gathers the wafer print window data. In addition, the other purpose is getting
exactly the same process condition of five kinds MoSi profile in both mask house and lithography of wafer
manufacturing Fab. The mask layout pattern is poly layer of logical 90 nm generation that is more critical among
all of lithography and was exposed by 193nm ArF.Then, we offer the effected level between absorber profile
and lithography process window. The process window of different SWA pattern will be compare to check the
relationship between process windows and mask profile. We also investigate how the profile affects the optical
Photomask blank flatness is more important for wafer lithography so far. In view of economic and capital concern, venders of mask blank always provide several level flatness of blank what mask house request. And the wafer fabricators would request the flatter photomask to fit the next generation requirement. The topography effect of photomask should be a contribution of lithography process window. The effect includes quartz substrate flatness and distortion and the film of Cr and MoSi deposit. Besides, the Mask blanks have several shapes that are flat, concave and convex. Reducing the effect from mask is the main consideration of depth of focus improvement. In this study, we made two masks of different type, 0.5T and 2.5T. Flatness measurement is directly provided by interferometer. To verify the effect between mask blank flatness and wafer printing window. Furthermore, we also check patterned mask effect of flatness. The pattern we use is poly layer of logical 90 nm generation that is more critical among all of lithography process and was exposed by 193nm ArF environment. Primary purpose of the ADI (after develop inspection) performance concern is process window of wafer print. Then, we offer the effected level between mask blank flatness and lithography process window.
CPL technology is one of the powerful methods for Resolution Enhancement Technology. With high NA and strong off-axis illumination CPL has a very high resolution and is capable of printing complex 2D patterns. Image using off-axis illumination with an attenuated phase shift mask can also improve process latitude. We can combine two technologies in one mask with same off-axis illumination condition to have more flexible application. Normally CPL technology is applied in binary mask and Qz is etched for 180 degree phase. To fulfill this hybrid mask we can apply Qz etch in current normal attenuate PSM blank and E-Beam 2nd writing is also can be applied for the zebra structure. To form the different application in different area we use 5 times writing in this hybrid mask process. Also the Qz etching process is very important because the Qz etching is strongly related to the Cr-Mosi-Qz three layer profile. So a L9 DOE has been applied for Qz etching parameter fine tuning. We will optimize the phase uniformity, phase linearity, profile, CD linearity and CD proximity through the DOE.
In this paper we describe, from the user's point of view, how Inverse Lithography Technology (ILT) differs from Optical Proximity Correction (OPC). We discuss some specifics of ILT at chip-scale. We show simulation and experimental results from 90nm and 65nm semiconductor nodes, comparing results from ILT-generated masks and OPC-generated masks for real-life layouts, in a production environment. In addition, we discuss issues related to complexity and manufacturability of ILT-generated masks.
Chemically amplified resists, CAR, and 50kV e-beam writers have been applied for the most advance mask manufacturing. To fulfill the requirement of 65nm generation a good performance resist played an important role. In this work, two advanced positive and negative CAR resist has been evaluated for 65nm photomask process with a 50kV e-beam pattern generator in an advanced process line. For 65nm node not only the resolution is needed to be improved but also the cirtical dimension(CD) control will be more critical than previous generation. So the evaluation is focus on the CD performance, resolution, profile, e-beam sensitivity, line edge roughness(LER), etc.
To extend the application of ArF exposure tool, CPL is one of the most powerful technologies for the resolution enhancement. From previous study, the 2nd level writing by E-Beam writer has been developed to ensure the manufacturability of CPL process. To fulfill the application of CPL Mask, we implemented this technology for 65nm DRAM patterning. First we studied the performance and characteristics of CPL mask with optimized exposure illumination setting for the desired pattern and dimension of 65nm DRAM. Then the mask data for CPL mask manufacture has been generated by modeled pattern decomposition approach together with rule and modeled OPC. This was accomplished by using an engine named MaskWeaver. For the manufacture of CPL mask, we used a binary mask and the Qz was etched for the 180 degrees phase difference. We utilized a 2nd level writing by an E-Beam writer to make the zebra pattern that was generated by the engine for the optimized patterning performance. The exposure tool we utilized for the verification of wafer patterning is an advanced 193nm exposure system. The process performance indexes such as MEEF, process window, CD uniformity were collected to show the capability of CPL process. Also, simulation and empirical data were compared to verify the performance of CPL technology. So by using an optimized CPL technology included mask data generation skill, mask making specifications, and ArF illumination optimization, we can meet the manufacture requirement of 65nm DRAM.
The chromeless phase lithography (CPL) is a potential technology for low k1 optical image. For the CPL technology, we can control the local transmission rate to get optimized through pitch imaging performance. The CPL use zebra pattern to manipulate the pattern local transmission as a tri-tone structure in mask manufacturing. It needs the 2nd level writing to create the zebra pattern. The zebra pattern must be small enough not to be printed out and the 2nd writing overlay accuracy must keep within 40nm. The request is a challenge to E-beam 2nd writing function. The focus of this paper is in how to improve the overlay accuracy and get a precise pattern to form accurate pattern transmission. To fulfill this work several items have been done. To check the possibility of contamination in E-Beam chamber by the conductive layer coating we monitor the particle count in the E-Beam chamber before and after the coated blank load-unload. The conductivity of our conductive layer has been checked to eliminate the charging effect by optimizing film thickness. The dimension of alignment mark has also been optimized through experimentation. And finally we checked the PR remain to ensure sufficient process window in our etching process. To verify the performance of our process we check the 3D SEM picture. Also we use AIMs to prove the resolution improvement capability in CPL compared to the traditional methods-Binary mask and Half Tone mask. The achieved overlay accuracy and process can provide promising approach for NGL reticle manufacturing of CPL technology.
It is an important task in 65nm generation to reduce process CD loss to get better pattern resolution and CD performance. As we know the main process CD loss is the etch process. This study is mainly in Cr etching process. Process CD loss reduction is one of critical issues in 65nm generation photomask fabrication to improve pattern resolution and total CD performance. The CD loss is mainly determined by etching process. Cr etching process is particularly important because the process decide the CD performance for not only binary mask but also phase shift mask. So, we focused on Cr etching process in this study. For Cr etch, the masking material is a soft-etchable photo-resist. The resist behavior in the etch process strongly affects the Cr etching performance. In our study, the resist we used is Chemical Amplified Resist. We devoted to reduce the CD loss during etching process by optimizing the etching parameter through a designed experiment (DoE). And we studied about the relation of etching bias with the parameter and the relation of etching bias with other etching property. Then we discussed about the over-etching time with the bias loss. The etching uniformity is strongly affected in the plasma etch optimization, including proximity CD bias, CD radial, and Cr loading effect. So these factors will be checked throughout our optimization study.