In the process nodes of 10nm and below, the patterning complexity, along with multiple pattern processing and the
advance materials required, has in turn resulted in a need to optimize wafer alignment mark simulation capabilities in
order to achieve the required precision and accuracy for wafer alignment performance.
ASML’s Design for Control (D4C) application for wafer alignment mark design has been extended to support the
computational prediction of alignment mark performance for the latest alignment sensor on the TwinScan NXT:1980Di
platform and beyond. Additional new simulation functionality will also be introduced to enable aberration sensitivity
matching between the alignment mark and the device cell patterns. As a result, the design of more robust alignment
marks is achieved, extending simulation capabilities for the design of wafer alignment marks and the recommendation of
alignment recipe settings.
In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML’s Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.
Immersion lithography is being extended to the 20-nm and 14-nm node and the lithography performance requirements need to be tightened further to enable this shrink. In this paper we present an integral method to enable high-order fieldto- field corrections for both imaging and overlay, and we show that this method improves the performance with 20% - 50%. The lithography architecture we build for these higher order corrections connects the dynamic scanner actuators with the angle resolved scatterometer via a separate application server. Improvements of CD uniformity are based on enabling the use of freeform intra-field dose actuator and field-to-field control of focus. The feedback control loop uses CD and focus targets placed on the production mask. For the overlay metrology we use small in-die diffraction based overlay targets. Improvements of overlay are based on using the high order intra-field correction actuators on a field-tofield basis. We use this to reduce the machine matching error, extending the heating control and extending the correction capability for process induced errors.