This work addresses the difficulties in creating a manufacturable M2 layer based on an SADP process for N10/N7 and proposes a couple of solutions. For the N10 design, we opted for a line staggering approach in which each line-end ends on a contact. We highlight the challenges to obtain a reasonable process window, both in simulation as on based on exposures on wafer. The main challenges come from a very complex keep mask, consisting of complicated 2D structures which are very challenging for 193i litho. Therefore, we propose a solution in which we perform a traditional LELE process on top of a mandrel layer. Towards N7 we show that a line staggering approach starts to break down and design needs to allow better process window for lithography by having metal lines ending in an aligned fashion. has many challenges and we propose to switch to a line cut approach. A more lithography friendly approach is needed for design where the lines end at aligned points so that the process window can be enhanced.
The density requirement expected for the 10nm node continues to increase the pressure on patterning. With the frontend of line adopting a regular layout (mostly unidirectional), most of the complexity needed for a functional chip ends up in the interconnect layer and Metal1. Assuming that Extreme Ultra Violet Lithography (EUVL) will not be ready for the early stage of 10nm production but only for high volume manufacturing, we have studied how ArF immersion lithography can be extended for Metal1 to sustain the development of the technology as well as the early production phase, while at the same time remaining compatible with an EUVL single patterning solution. We show how close interaction between design, process and computational lithography leads to a Metal1 triple patterning solution using Negative Tone Development (NTD), and how the same design solution can be supported by EUVL single patterning. Particular attention will be paid to line end printability performance, both tip to tip and tip to line, as we believe it is a key parameter to define the best compromise between lithography performance and design density.