In this paper, we present a family of large format CIS’s designed for dental x-ray applications. The CIS areas vary from
small 31.5mm x 20.1mm, to medium 34.1mm x 26.3mm, to large 37.1mm x 26.3mm. Pixel size is 19.5um x 19.5um.
The sensor family was fabricated in a 0.18um CIS process. Stitching is used in the CIS fabrication for the medium and
large size sensors. We present the CIS and detector system design that includes pixel circuitry, readout circuitry, x-ray
trigger mechanism, scintillator, and the camera electronics. We also present characterization results including the
detector performances under both visible light and x-ray radiation.
In this paper, we present an overview of high-performance CMOS image sensor products developed at BAE SYSTEMS
Imaging Solutions designed to satisfy the increasingly challenging technical requirements for image sensors used in
advanced scientific, industrial, and low light imaging applications. We discuss the design and present the test results of a
family of image sensors tailored for high imaging performance and capable of delivering sub-electron readout noise,
high dynamic range, low power, high frame rates, and high sensitivity. We briefly review the performance of the
CIS2051, a 5.5-Mpixel image sensor, which represents our first commercial CMOS image sensor product that
demonstrates the potential of our technology, then we present the performance characteristics of the CIS1021, a full HD
format CMOS image sensor capable of delivering sub-electron read noise performance at 50 fps frame rate at full HD
resolution. We also review the performance of the CIS1042, a 4-Mpixel image sensor which offers better than 70% QE
@ 600nm combined with better than 91dB intra scene dynamic range and about 1 e- read noise at 100 fps frame rate at
As bio-technology transitions from research and development to high volume production, dramatic improvements in
image sensor performance will be required to support the throughput and cost requirements of this market. This includes
higher resolution, higher frame rates, higher quantum efficiencies, increased system integration, lower read-noise, and
lower device costs. We present the performance of a recently developed low noise 2048(H) x 2048(V) CMOS image
sensor optimized for scientific applications such as life science imaging, microscopy, as well as industrial inspection
applications. The sensor architecture consists of two identical halves which can be operated independently and the
imaging array consists of 4T pixels with pinned photodiodes on a 6.5μm pitch with integrated micro-lens. The operation
of the sensor is programmable through a SPI interface. The measured peak quantum efficiency of the sensor is 73% at
600nm, and the read noise is about 1.1e- RMS at 100 fps data rate. The sensor features dual gain column parallel ouput
amplifiers with 11-bit single slope ADCs. The full well capacity is greater than 36ke-, the dark current is less than
7pA/cm2 at 20°C. The sensor achieves an intra-scene linear dynamic range of greater than 91dB (36000:1) at room
In this paper, we present a CMOS digital intra-oral sensor for x-ray radiography. The sensor system consists of a custom
CMOS imager, custom scintillator/fiber optics plate, camera timing and digital control electronics, and direct USB
communication. The CMOS imager contains 1700 x 1346 pixels. The pixel size is 19.5um x 19.5um. The imager was
fabricated with a 0.18um CMOS imaging process. The sensor and CMOS imager design features chamfered corners for
patient comfort. All camera functions were integrated within the sensor housing and a standard USB cable was used to
directly connect the intra-oral sensor to the host computer. The sensor demonstrated wide dynamic range from 5uGy to
1300uGy and high image quality with a SNR of greater than 160 at 400uGy dose. The sensor has a spatial resolution
more than 20 lp/mm.
Digital photographers continuously demand more performance from their equipment. Digital camera performance is defined by a set of parameters including dynamic range, noise, frame rate, resolution, and color. Amongst these parameters dynamic range is becoming increasingly more important. This is true because the human eye typically has a wider dynamic range than a digital camera. In this paper we define dynamic range as the ratio of the maximum to the minimum signal that can be detected. At the heart of all digital cameras is either a CCD or a CMOS image sensor (CIS). The dynamic range of the sensor typically limits the dynamic range of the camera.
In this paper we review five CIS architectures that are designed to improved dynamic range. We start by reviewing standard CCD and CIS architectures and then present a simple sensor model. Using this model we show how signal to noise ratio (SNR) can be used to evaluate different wide dynamic range (WDR) sensor architectures. Then we sequentially review five different wide dynamic range techniques. The first WDR technique is multiple gains, and the second technique is non-linear pixel response. The third technique is variable exposure, and the forth technique is well capacity recycling. The fifth and final technique is time to saturation. For each of these techniques we present the pixel level circuitry and its advantages and disadvantages. Furthermore, all of these techniques are compared based on SNR and implementation complex. We discuss how implementation complexity affects signal processing in a digital camera, and other parameters in the sensor such as quantum efficiency and read noise. We conclude with a few summary comments.
We evaluate the effects of 10 MeV proton irradiation on the performance of a 5.5 Mpixel scientific grade CMOS image
sensor based on a 5T pixel architecture with pinned photodiode and transfer gate. The sensor has on-chip dual column
level amplifiers and 11-bit single slope analog to digital converters (ADC) for high speed readout and wide dynamic
range. The operation of the sensor is programmable and controlled by on-chip digital control modules. Since the image
sensor features two identical halves capable of operating independently, we used a mask to expose only one half of the
sensor to the proton beam, leaving the other half intact to serve as a reference. In addition, the pixel array and the digital
logic control section were irradiated separately, at dose rates varying from 4 rad/s to 367 rad/s, for a total accumulated
dose of 146 krad(Si) to assess the radiation effects on these key components of the image sensor. We report the resulting
damage effects on the performance of the sensor including increase in dark current, temporal noise, dark spikes,
transient effects and latch-up. The dark signal increased by about 55 e-/pixel after exposure to 14 krad (Si) and the dark
noise increased from about 2.75e- to 6.5e-. While the number of hot pixels increased by 6 percent and the dark signal
non uniformity degraded, no catastrophic failure mechanisms were observed during the tests, and the sensor did not
suffer from functional failures.
In this paper we present radiation studies performed on a low-noise, high-speed, largearea
CMOS image sensor (CIS) based on the 0.18 μm CMOS process. The sensor has
2560(H) x 2160(V) pixels with a readout speed of 100 frames/sec and a readout noise of
less than 2 e- rms. The sensor features 5T pinned photodiode pixels on a 6.5 μm pitch. In
order to measure the impact of radiation exposure on the sensor performance, the device
was subjected to x-ray exposure of 50 kRads of incident radiation using a broad band 50
KVP x-ray source to assess Total Ionizing Dose (TID) sensitivity. The active area and the
digital control block and amplification circuitry were separately irradiated to evaluate the
damage to each. Dark data was captured as a function of radiation dose in order to
measure dark current and offset changes in the signal.
In this paper we present radiation studies performed on a low-noise, high-speed, large-area CMOS
image sensor (CIS) based on the 0.18 μm CMOS process. The sensor has 2560(H) × 2160(V) pixels
with a readout speed of 100 frames/sec and a readout noise of less than 2 e- rms. The sensor features
5T pinned photodiode pixels on a 6.5 um pitch. In order to measure the impact of radiation exposure
on the sensor performance, the device was subjected to x-ray exposure of 50 kRads of incident
radiation using a broad band 50 KVP x-ray source to assess Total Ionizing Dose (TID) sensitivity.
The active area and the digital control block and amplification circuitry were separately irradiated to
evaluate the damage to each. Dark data was captured as a function of radiation dose in order to
measure dark current and offset changes in the signal.
We present the performance of a CMOS image sensor optimized for next generation fused day/night vision systems.
The device features 5T pixels with pinned photodiodes on a 6.5μm pitch with integrated micro-lens. The 5T pixel
architecture enables both correlated double sampling (CDS) to reduce noise for night time operation, and a lateral antiblooming
drain for day time operation. The measured peak quantum efficiency of the sensor is above 55% at 600nm,
and the median read noise is less than 1e- RMS at room temperature. The sensor features dual gain 11-bit data output
ports and supports 30 fps and 60 fps. The full well capacity is greater than 30ke-, the dark current is less than 3.8pA/cm2
at 20ºC, and the MTF at 77 lp/mm is 0.4 at 550nm. The sensor also achieves an intra-scene linear dynamic range of
greater than 90dB (30000:1) for night time operation, and an inter-scene linear dynamic range of greater than 150dB for
complete day/night operability.
In this paper we describe a 5.5Mpixel 100 frames/sec wide-dynamic-range low-noise CMOS image sensor (CIS)
designed for scientific applications. The sensor has 6.5μm pitch 5T pixels with pinned photodiodes and integrated
microlenses. The 5T pixel architecture enables low noise rolling and global shutter operation. The measured peak
quantum efficiency of the sensor is greater than 55% at 550nm, the Nyquist MTF is greater than 0.4 at 550nm, and the
linear full well capacity is greater than 35ke-. The measured rolling and global shutter readout noise are 1.28e- RMS
and 2.54e- RMS respectively at 30 f/s and 20°C. The pinned photodiode dark current is less than 3.8pA/cm2 at 20°C.
The sensor achieves an intra-scene linear dynamic range in rolling shutter operation of greater than 86dB (20000:1) at
room temperature. In global shutter readout the shutter efficiency is greater than 1000:1 with 500nm illumination.
The field of ultrafast x-ray science is flourishing, driven by emerging synchrotron sources (e.g., time-slice storage rings, energy recovery linacs, free electron lasers) capable of fine time resolution. New hybrid x-ray detectors are under development in order to exploit these new capabilities.
This paper describes the development of a 2160 x 2560 CMOS image sensor (CIS) system with a 6.5 µm pitch optimized for time-resolved x-ray scattering studies. The system is single photon quantum limited from 8 keV to 20 keV. It has a wide dynamic range and can operate at 100 Hz full-frame and at higher frequencies using a region-of-interest (ROI) readout. Fundamental metrics of linearity, dynamic range, spatial resolution, conversion gain, sensitivity and Detective Quantum Efficiency are estimated. Experimental time-resolved data are also presented.
In this paper we present a VNIR solid state sensor technology suitable for next generation fused night vision systems.
This technology is based on a highly optimized low power 0.18um CMOS image sensor (CIS) process. We describe a
320(H) x 240(V) pixel prototype sensor based on this technology. The sensor features 5T pixels with pinned
photodiodes on a 6.5μm pitch with integrated micro-lens. The 5T pixel architecture enables both correlated double
sampling (CDS) and a lateral anti-blooming drain. The measured peak quantum efficiency of the sensor is greater than
50% at 600nm, and the read noise is less than 1e- RMS at room temperature. The sensor does not have any
multiplicative noise. The full well capacity is greater than 40ke-, the dark current is less than 3.8pA/cm2 at 20ºC, and the
MTF at 77 lp/mm is 0.4 at 600nm. The sensor also achieves an intra-scene linear dynamic range of greater than 90dB
(30000:1) at room temperature.
CCDs have been the primary sensor in imaging systems for x-ray diffraction and imaging
applications in recent years. CCDs have met the fundamental requirements of low noise,
high-sensitivity, high dynamic range and spatial resolution necessary for these scientific
applications. State-of-the-art CMOS image sensor (CIS) technology has experienced
dramatic improvements recently and their performance is rivaling or surpassing that of
most CCDs. The advancement of CIS technology is at an ever-accelerating pace and is
driven by the multi-billion dollar consumer market. There are several advantages of CIS
over traditional CCDs and other solid-state imaging devices; they include low power,
high-speed operation, system-on-chip integration and lower manufacturing costs. The
combination of superior imaging performance and system advantages makes CIS a good
candidate for high-sensitivity imaging system development.
This paper will describe a 1344 x 1212 CIS imaging system with a 19.5μm pitch
optimized for x-ray scattering studies at high-energies. Fundamental metrics of linearity,
dynamic range, spatial resolution, conversion gain, sensitivity are estimated. The
Detective Quantum Efficiency (DQE) is also estimated. Representative x-ray diffraction
images are presented. Diffraction images are compared against a CCD-based imaging
We present the design and test results of a prototype 4T CMOS image sensor fabricated in 0.18-μm technology
featuring 20 different 6.5 μm pixel pitch designs. We review the measured data which clearly show the impact of the
pixel topologies on sensor performance parameters such as conversion gain, read noise, dark current, full well capacity,
non-linearity, PRNU, DSNU, image lag, QE and MTF. Read noise of less than 1.5e- rms and peak QE greater than
70%, with microlens, are reported.
A multitude of scientific, medical, and defense applications require imaging at low light level. Examples include:
live-cell fluorescence microscopy, wavefront sensing for adaptive optics, and night vision. To address these
applications low light level sensors need to have low noise, high quantum efficiency, low lag, high MTF, high
frame rates, and low power. Over the past 50 years a variety of techniques have been developed to analyze
and compare these technologies. The purpose of this paper is to develop an analytical method for estimating
limiting resolution of low light level sensors and cameras. We present a communication theory based model
that is designed to enable rapid evaluation of low light level sensors and aid in the understanding of how these
systems operate. This model can be applied to electron multiplied CCDs, electron bombarded CMOS sensors,
and hybrid CCD/CMOS sensors. In addition we also describe a device physics based low light level camera
simulator. We compare our model to the camera simulator and show that the model can be used to accurately
predict camera performance. In addition the computational complexity of our model is 1/150 of a complete low
light level camera simulator.
We present a CCD / CMOS hybrid focal plane array (FPA) for low light level imaging applications. The hybrid approach combines the best of CCD imaging characteristics (e.g. high quantum efficiency, low dark current, excellent uniformity, and low pixel cross talk) with the high speed, low power and ultra-low read noise of CMOS readout technology. The FPA is comprised of two CMOS readout integrated circuits (ROIC) that are bump bonded to a CCD imaging substrate. Each ROIC is an array of Capacitive Transimpedence Amplifiers (CTIA) that connect to the CCD columns via indium bumps. The proposed column parallel readout architecture eliminates the slow speed, high noise, and high power limitations of a conventional CCD. This results in a compact, low power, ultra-sensitive solid-state FPA that can be used in low light level applications such as live-cell microscopy and security cameras at room temperature operation. The prototype FPA has a 1280×1024 format with 12-um square pixels. Measured dark current is less than 5.8 pA/cm2 at room temperature and the overall read noise is as low as 2.9e at 30 frames/sec.
This paper describes an in-situ pixel source follower power spectral density (PSD) measurement method that does not require any specialized test equipment. This method requires a dual port CMOS image sensor with analog outputs that allow differential time series noise measurements. We describe the sensor circuits and measurement techniques used for collecting data. We derive an estimator for the PSD based on the measured data. We also present a technique for estimating the confidence interval of the PSD based on Bootstrap re-sampling. Using our estimate of the PSD, we derive estimators for the SPICE NLEV3 1/f noise model parameters AF and KF. We also determine confidence intervals for these estimators. Using this method we present the estimated source follower PSD for a CMOS image sensor fabricated in a 0.18μm CMOS process with 3.3μm X 3.3μm pixels. We also present the estimated values of AF and KF based on the estimated PSD.
As the fastest-growing consumer electronics device in history, the camera phone has evolved from a toy into a real camera that competes with the compact digital camera in image quality. Due to severe constraints in cost and size, one key question that remains unanswered for camera phones is: how good does the image quality need to be so that resource can be allocated most efficiently. In this paper, we have tried to find the color processing tolerance through a study of 24 digital cameras from six manufacturers under five different light sources. We measured both the inter-brand (across manufacturers) and intra-brand (within manufacturers) mean and standard deviation for white balance and color reproduction. The white balance results showed that most cameras didn’t follow the complete white balance model. The difference between the captured white patch and the display white point increased when the correlated color temperature (CCT) of the illuminant was further away from 6500K. The standard deviation of the red/green and blue/green ratios for the white patch also increased when the illuminant was further away from 6500K. The color reproduction results revealed a similar trend for the inter-brand and intra-brand chromatic difference of the color patches. The average inter-brand chromatic difference increased from 3.87 ΔE units for the Δ65 light (6500K) to 10.13 ΔE units for the Horizon light (2300K).
This paper describes a 2048x1 linear image sensor implemented in a 0.35 μm 4M1P CMOS process that uses a low fixed pattern noise capacitive transimpedance amplifier (LFPN CTIA) pixel architecture. The pixel also includes circuitry for reducing 1/f noise, correlated double sampling, electronic shuttering, and a horizontal anti-blooming drain. High speed non-destructive readout of the sensor is achieved by using a hierarchical readout structure with two output ports. Using a JTAG interface the sensor can be programmed to operate in multiple readout modes. In the fastest readout mode, ROI, the sensor achieves 90Mpixel/sec (43.4Klines/sec) with 14e- RMS read noise. In the lowest noise mode, MRDI, with 13x oversampling of each pixel the sensor achieves 2.7Klines/sec with 1.2e- RMS read noise.
In this paper we introduce a low fixed pattern noise (LFPN) capacitive transimpedance amplifier (CTIA) for active pixel CMOS image sensors (APS) with high switchable gain and low read noise. The LFPN CTIA APS uses a switched capacitor voltage divider feedback circuit to achieve high sensitivity, low gain FPN, and low read noise. This paper discusses the operation of the LFPN CTIA APS, and presents a theoretical analysis of its gain FPN and read noise. We do not analyze the effect of 1/f noise, since it is typically much smaller than the thermal and shot noise effects. Monte Carlo simulation of gain FPN and SPICE simulation of read noise are also presented. For a 0.35 micrometers CMOS LFPN CTIA at room temperature and an output data rate of 16Mpixel/sec, we show that the pixel amplifier gain FPN is less than 0.0064, where FPN is defined as the ratio of standard deviation to mean. The read noise and dynamic range are less than 3 electrons RMS and greater than 90dB respectively. We find that theory and simulated results match closely.
Pixel reset noise sets the fundamental detection limit on photodiode based CMOS image sensors. Reset noise in standard active pixel sensor (APS) is well understood and is of order kT/C. In this paper we present a new technique for resetting photodiodes, called active reset, which reduces reset noise without adding lag. Active reset can be applied to standard APS. Active reset uses bandlimiting and capacitive feedback to reduce reset noise. This paper discusses the operation of an active reset pixel, and presents an analysis of lag and noise. Measured results from a 6 transistor per pixel 0.35 micrometers CMOS implementation are presented. Measured results show that reset noise can be reduced to less than kT/18C using active reset. We find that theory simulation and measured results all match closely.
Temporal noise sets a fundamental limit on image sensor performance, especially under low illumination and in video applications. In a CCD image sensor, temporal noise is well studied and characterized. It is primarily due to the photodetector shot noise and the thermal and 1/f noise of the output charge to voltage amplifier. In a CMOS APS several addition sources contribute to temporal noise, including the noise due to the pixel rest, follower, and access transistors. The analysis of noise is further complicated by the nonlinearity of the APS charge to voltage characteristics, which is becoming more pronounced as CMOS technology scales, and the fact that the reset transistor operates below threshold for most of the reset time. The paper presents an accurate analysis of temporal noise in APS. We analyze the noise for each stage of the sensor operation, and identify the noise contribution from each source. We analyze noise due to photodetector shot noise taking nonlinearity into consideration. We find that nonlinearity improves SNR reset transistor shot noise is at most half the commonly quoted value. Using HSPICE simulation, we find the noise due to the follower and access transistors. As expected we find that at low illumination reset noise dominates, while at high illumination photodetector shot noise dominates. Finally, we present experimental results from test structures fabricated in 0.35(mu) CMOS processes. We find that both measured peak SNR and reset noise values match well with the results of our analysis.
Techniques for characterizing CCD imagers have been developed over many years. These techniques have been recently modified and extended to CMOS PPS and APS imagers. With the scaling of CMOS technology, an increasing number of transistors can be added to each pixel. A promising direction to utilize these transistors is to perform pixel level ADC. The authors have designed and prototyped two imagers with pixel level Nyquist rate ADC. The ADCs operate in parallel and output data one bit at a time. The data is read out of the imager array one bit plane at a time in a manner similar to a digital memory. Existing characterization techniques could not be directly used for these imagers, however, since there is no facility to read out the analog pixel values before ADC, and the ADC resolution is limited to only 8 bits. Fortunately, the ADCs are fully testable electrically without the need for any light or optics. This makes it possible obtain the ADC transfer curve, which greatly simplifies characterization. In this paper we describe how we characterize our pixel level ADC imagers. To estimate QE, we measure the imager photon to DN transfer curve and the ADC transfer curve. We find that both curves are quite linear.Using an estimate of the sense node capacitance we then estimate sensitivity, and QE. To estimate FPN we model it as an outcome of the sum of two uncorrelated random processes, one representing the ADC FPN, and the other representing the photodetector FPN, and develop estimators for the model parameters form imager data under uniform illumination. We report characterization result for a 640 by 512 imager, which was fabricated in a 0.35 micrometers standard digital CMOS process.
Pixel level processing promises many significant advantages including high SNR, low power, and the ability to adapt image capture and processing to different environments by processing signals during integration. However, the severe limitation on pixel size has precluded its mainstream use. In this paper we argue that CMOS technology scaling will make pixel level processing increasingly popular. Since pixel size is limited primarily by optical and light collection considerations, as CMOS technology scales, an increasing number of transistors can be integrated at the pixel. We first demonstrate that our argument is supported by the evolution of CMOS image sensor from PPS to APS. We then briefly survey existing work on analog pixel level processing an d pixel level ADC. We classify analog processing into intrapixel and interpixel. Intrapixel processing is mainly used to improve sensor performance, while interpixel processing is used to perform early vision processing. We briefly describe the operation and architecture of our recently developed pixel level MCBS ADC. Finally we discuss future directions in pixel level processing. We argue that interpixel analog processing is not likely to become mainstream even for computational sensors due to the poor scaling popular since it minimizes analog processing, and requires only simple and imprecise circuits to implement. We then discuss the inclusion of digital memory and interpixel digital processing in future technologies to implement programmable digital pixel sensors.
Two techniques for performing pixel level analog to digital conversion (ADC) are reviewed. The first is an over-sampling technique which uses a one bit first order (Sigma) (Delta) modulator for each 2 X 2 block of pixels to directly convert photocharge to bits. Each modulator is implemented using 17 transistors. The second technique is a Nyquist rate multi-channel-bit-serial (MCBS) ADC. The technique use successive comparisons to convert the pixel voltage to bits. Results obtained from implementations of these ADC techniques are presented. The techniques are compared based on size, charge handling capacity, FPN, noise sensitivity, data throughput, quantization, memory/processing, and power dissipation requirements for both visible an dIR imagers. From the comparison it appears that the (Sigma) (Delta) ADC is better suited to IR imagers, while the MCBS ADC is better suited to imagers in the visible range.
Fixed pattern noise (FPN) for a CCD sensor is modeled as a sample of a spatial white noise process. This model is, however, not adequate for characterizing FPN in CMOS sensors, since the redout circuitry of CMOS sensors and CCDs are very different. The paper presents a model for CMOS FPN as the sum of two components: a column and a pixel component. Each component is modeled by a first order isotropic autoregressive random process, and each component. Each component is modeled by a first order isotropic autoregressive random process, and each component is assumed to be uncorrelated with the other. The parameters of the processes characterize each component of the FPN and the correlations between neighboring pixels and neighboring columns for a batch of sensor. We show how to estimate the model parameters from a set of measurements, and report estimates for 64 X 64 passive pixel sensor (PPS) and active pixel sensor (APS) test structures implemented in a 0.35 micron CMOS process. High spatial correlations between pixel components were measured for the PPS structures, and between the column components in both PPS and APS. The APS pixel components were uncorrelated.
The standard method for measuring QE for a CCD sensor is not adequate for CMOS APS since it does not take into consideration the random offset, gain variations, and nonlinearity introduced by the APS readout circuits. The paper presents a new method to accurately estimate QE of an APS. Instead of varying illumination as in the CCD method, illumination is kept constant and the pixel output is continuously observed - sampling at regular intervals. This makes it possible to eliminate random offset. The experiment is repeated multiple times to obtain good estimates of the pixel output mean and variance at each sample time. The sensor response is approximated by a piecewise linear function and using the Poisson statistics of shot noise gain, charge and read noise are estimated for each line segment. This procedure is repeated at no illumination so that dark charge may be estimated and subtracted from the total charge estimates. The method can also be used to estimate readout noise and gain FPN. Results from 64 X 64 pixel APS test structures implemented in a 0.35 micrometers CMOS process are reported. Using 6 different chips and 16 pixels per chip QE equals 0.37, gain FPN equals 2 percent, dark charge equals 832e-, and readout noise equals 40e-, are estimated.
A set of test structures designed to characterize and compare the performance of CMOS passive and active pixel image sensors is presented. The test structures are deigned so that they can be rapidly ported from one process to another. They are also designed so that individual photodetectors and pixel circuits as well as entire image sensor arrays can be characterized and compared based on: quantum efficiency, spectral response, fixed pattern noise, sensitivity, blooming, input referred read noise, reduction of quantum efficiency caused by silicide/salicide, lag, digital switching noise sensitivity, impact ionization noise sensitivity, dynamic range, and temperature dependency of all measured parameters. Four test chips that include a variety of these structures have been built in two different 0.35 micrometer CMOS processes. The test chips include nineteen types of individual photodetectors and thirty eight types of 64 by 64 pixel arrays. The test methodology and preliminary test results from these chips are presented.