Line edge roughness (LER) reduction is critical during the patterning process definition and development, as the critical dimension (CD) and pitch scale in advanced semiconductor technology nodes. In this paper, we will focus on a 7nm self-aligned double patterning (SADP) process for use in back end of line (BEOL). Specifically, we will investigate LER from various lithography options and how LER changes through downstream processes, including mandrel etch, spacer deposition, hard mask open, dielectric etch and wet clean. We characterized LER as a function of several mandrel etch parameters such as O2 flow rate, over etch rate percentage and polymer deposition rates. We also characterized LER response to dielectric etch parameters and found that while some etch processes may smooth high frequency LER, there are additional cases where the final etch and wet-clean increased LER and line wiggling. Overall, we observed that lithography is the primary source of LER and we have the opportunity to reduce LER by both design and process optimization. In this paper we focused on characterization of a standard logic cell with varied CD and pitch. We looked through various designs, retargeting as well as both negative tone developer (NTD) and positive tone developer (PTD) resists for the LER reduction. We also analyzed the image log slope (ILS) of each corresponding edge and the process windows of the resist candidates. We concluded that ILS improvement and resist selection are the primary knobs to reduce LER. With optimization, we can achieve LER close to the process assumption targets for 7nm technology node. Further LER reduction techniques are definitely needed in both 7nm and future nodes even with migration from 193nm to EUV lithography.
When technology node transitions to 14nm and beyond, multi-patterning technique including litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) with optical lithography is required to achieve device scaling until extreme ultraviolet (EUV) comes into full production. Although LELE and SADP are widely used and well-studied for line-space layers, the challenge of contact layers still remains unknown. In addition, process window (PW) and pattern defects are often characterized with lithography printability only before 7nm. However, when the gate length is pushed to the limitation of immersion lithography, hard mask open etch (HMO) also needs to be studied along with lithography printability to further optimize overall patterning process window (PW). In this paper, we first studied several optical proximity correction (OPC) techniques such as source-mask optimization (SMO) and sub-resolution assist features (SRAF) to improve PW. We then characterized the patterning PW on several patterning defects including single-layer bridging, multi-layer bridging, missing contact, unlanded contact, and extra contact by tuning develop CD (DCD) and HMO CD (MCD).
SMO such as illumination source and projection lens wavefront has been extensively used to enlarge depth of focus (DoF). Two different XY polarizations sources were optimized via SMO and were verified on silicon based on overlap process window and mask error enhancement factor (MEEF). Both sources have achieved <90nm lithography PW and <3 MEEF for the selected SRAM and logic designs. The effect of SRAF size on patterning PW were studied by obtaining DoF and exposure latitude (EL) post develop and post HMO. DoF was enlarged by 20nm when increasing SRAF size; however, EL was reduced by 6% post develop and by 2% only post HMO, suggesting patterning PW should be studied at post HMO instead of post develop.
When characterizing multi-patterning PW, two types of defects need to be considered: type 1) single-layer bridging and missing contact driven by lithography only; type 2) multi-layer bridging, unlanded contact, and extra pattern driven by both lithography and HMO. Type 1 defects were studied by lithography printability from focus-exposure matrix for different targets (dense/semi-iso/iso) and maximum lithography PW was achieved by adjusting DCD. Type 2 defects were studied by adjusting both DCD and MCD (etch bias). Missing contact was improved by 20x and unlanded contact was improve by 5x when DCD was increased by 8%; however, multi-layer bridging was worsen by 10x, which can be improved by decreasing MCD by 8%. As a result, overall patterning PW can only be obtained by combining lithography PW and HMO optimization.
Proc. SPIE. 10146, Advances in Patterning Materials and Processes XXXIV
KEYWORDS: Semiconductors, Optical lithography, Etching, Metals, Scanning electron microscopy, Atomic layer deposition, Photomasks, Critical dimension metrology, Reactive ion etching, Semiconducting wafers, Back end of line
Abstract Multiple patterning employing etch shrink extends the scaling of hardmask open CD (HCD) to sub-50nm regime. A plasma-assisted shrink technique is primarily used in the back-end-of-line (BEOL) however it faces major challenges such as the line end shortening (LES) and large critical dimension iso-dense bias (IDB). In order to mitigate these two problems we apply an atomic layer deposition (ALD) spacer shrink process at 10nm metal interconnect layer with sub-20nm minimum half-pitch. As a result we observed 8nm LES improvement in tip-to-tip (T2T) two-dimensional (2D) structures, and 5nm IDB reduction in one-dimensional (1D) structures. These improvements suggest that the ALD spacer shrink can contribute to more precise CD control in multiple patterning.
The use of different illumination source shapes and multipatterning processes used to generate sub–40-nm images can create image placement errors level to level, resulting in significant intrafield overlay errors. These errors arise because of the impact of the different pupil shapes on lens aberrations resolving into image placement errors as well as because different tools will react differently to the same pupil shapes. We compare the impact of two extreme illumination sources on intrafield image placement and its effect on overall pattern overlay. We also discuss a method to empirically isolate and measure the amount of intrafield overlay distortion relative to a reference illumination source and then use the results to correct the resultant image placement errors.
Prime silicon wafers are ideal substrates for lithographic patterning, with tight flatness specifications for focus control. Process engineers are painfully aware that in-process product wafers can substantially depart from this ideal substrate. Wafer processing can induce non-flatness leading to focus problems, or distort the wafer leading to overlay issues. Thus processes from outside the lithography sector can impact yield by ruining lithographic pattern quality. Double-sided optical interferometric metrology is the standard method to assess the flatness of blank silicon wafers. In the last several years, a similar Patterned Wafer Geometry (PWG) metrology tool is able to measure in-process patterned wafers. The apparent surface seen by an interferometer may be different than the true surface due to transparent thin films, a discrepancy that we call "false topography". Modeling results will demonstrate the use of a thin opaque film to reduce the problem. PWG metrology offers compelling advantages for the practical investigation of process-induced focus and overlay problems. The paper will include several examples of process learning from PWG metrology.
The use of extreme freeform illumination conditions and multi patterning processes used to generate sub 40nm images can result in significant intra-field overlay errors. When levels with differing illumination conditions are aligned to each other, these intra-field distortions can result in overlay errors which are uncorrectable using normal linear feedback corrections. <p> </p>We use a double exposure method, previously described by Minghetti  et al. to isolate and measure intra-field overlay distortions caused by tool lens signatures and different illumination conditions. A full field test reticle is used to create a dual level expose pattern. The same pattern is exposed twice, but with two different illumination conditions. The first exposure is done with a standard reference illumination. The second exposure is the target illumination condition. The test reticle has overlay target pairs that are measurable when the 2nd exposure is offset in the Y direction by the designed amount. This allows for a high density, 13x13, intra-field overlay measurement to be collected and modeled to determine 2<sup>nd</sup> and 3<sup>rd</sup> order intra-field terms. Since the resulting illumination and scanner lens specific intra field corrections are independent of field size, the sub-recipes can be applied to any product exposure independent of field size, which use the same illumination conditions as the test exposures. When the method is applied to all exposure levels in a product build cycle, the overlay errors contributed by the reference illumination condition cancel out. The remaining errors are due exclusively to the impact of the illumination condition on that scanner lens. <p> </p>Actual results correlated well with the model with more than 80% of the predicted overlay improvement being achieved.
As 193-nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28-nm technology nodes has been greatly facilitated by the just-in-time introduction of new process enablers that allow the support of flexible foundry-oriented ground rules alongside high-performance technology, without inhibiting migration to a single-pass patterning process. The incorporation of device-based performance metrics, along with rigorous patterning and structural variability studies, was critical in the evaluation of material innovation for improved resolution and CD shrink. Additionally, novel design changes for single patterning incorporating mask optimization efforts, along with new capability in data preparation, were assessed to allow for minimal impact of implementation of a single patterning contact process late in the 32-nm and 28-nm development cycles. In summary, this paper provides a comprehensive study of what it takes to turn a contact-level double-patterning process into a single-patterning process consisting of design and data manipulation, as well as wafer manufacturing aspects, together with many results.
The paper describes a process/design co-optimization effort based on an SRAM design to enable a single exposure
contact process for the 28nm technology half node.
As a start, a change to the wiring concept of the standard SRAM design was implemented. The resulting individual
contact layer elements may seem even more resolution critical to the casual observer. But in reality, the flexibility for
source-mask optimization had been significantly improved. In a second step, wafer targets and mask dimension options
(using various kinds of OPC methods and SRAF strategies) were run through several optimization iterations. This
included interlevel considerations due to stringent overlap requirements. Several promising SRAM design as well as
mask options were identified and experimentally verified to finally converge to an optimum mask and wafer target
layout. Said optimum solution still supports an automated OPC approach using standard EDA tools and off the shelf
In a last step, a 1Mbit electrically testable SRAM was designed and manufactured together with alternative SRAM
designs and process options.
After explaining the changes to the wiring of the SRAM design, the paper discusses in great detail various mask
optimization solutions and their consequences on wafer target and printability. Simulation and experimental results are
compared and the concluding optimized solution is explained. Furthermore, some key lithography and etch process
elements that became the single exposure process enabler are explained in more detail. Finally, the paper will take a look
at electrical results of the 1Mbit electrically testable SRAM as the ultimate proof of concept.
As 193 nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure
to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass
processes. Contact patterning for the 32/28 nm technology nodes has been greatly facilitated by just-in-time introduction
of new process enablers that allow the simultaneous support of flexible foundry-oriented ground rules alongside highperformance
technology, while also migrating to a single-pass patterning process. The incorporation of device based
performance metrics along with rigorous patterning and structural variability studies were critical in the evaluation of
material innovation for improved resolution and CD shrink along with novel data preparation flows utilizing aggressive
strategies for SRAF insertion and retargeting.
We discuss the lithographic qualification of a new type of binary mask blank consisting of an opaque layer of MoSi on a glass substrate, referred to simply as OMOG. First, OMOG lithographic performance will be compared to a previous chrome/MoSi/glass binary intensity mask (BIM) blank. Standard 70-nm chrome on class (COG) was not considered, as it failed to meet mask-making requirements. Theory and a series of simulation and experimental studies show OMOG to outperform BIM, particularly due to electromagnetic effects and optical proximity correction (OPC) predictability concerns, as OMOG behaves very similarly to the ideal thin mask approximation (TMA). A new TMA-predictability metric is defined as a means to compare mask blanks. We weigh the relative advantages and disadvantages of OMOG compared to 6% attenuated phase shifting. Although both mask blanks are likely sufficient for the 32-nm and 22-nm nodes, some differences exist and are described. Overall, however, of the blanks considered, it is concluded that OMOG provides the most robust and extendable imaging solution available for 32-nm and beyond.
Source optimization in optical lithography has been the subject of increased exploration in recent years [1-4], resulting in
the development of multiple techniques including global optimization of process window . The performance
advantages of source optimization have been demonstrated through theory, simulation, and experiment. This paper will
emphasize global optimization of sources over multiple patterns, e.g. co-optimization of critical SRAM cells and the
critical pitches of random logic, and implement global source optimization into current resolution enhancement
techniques (RETs). The effect on optimal source due to considering multiple patterns is investigated. We demonstrate
that optimal source for limited patterns does work for a large clip of layout. Through theoretical analysis and
simulations, we explain that only critical patterns and/or critical combinations of patterns determine the final optimal
source; for example those patterns that contain constraints which are active in the solution. Furthermore, we illustrate,
through theory and simulation, that pixelated sources have better performance than generic sources and that in general it
is impossible for generic sources to construct a truly optimal solution. Sensitivity, tool matching, and lens heating issues
for pixelated sources are also discussed in this paper. Finally, we use a RETs example with wafer data to demonstrate the
benefits of global source optimization.
Contact hole patterning and especially sub resolution assist feature (SRAF) insertion and optical proximity
correction (OPC) have become an extremely critical element of enabling continued shrink of CMOS
technology. These elements of mask generation are fundamental to the success of technology execution. As
off-axis illumination modes have been introduced to resolve smaller pitches, forbidden pitches emerge that
need to be considered in random logic layouts. Optimized placement of assist features for these pitches is
extremely important for overall process window and tolerance budget considerations. Several techniques
have recently been developed for model based SRAF optimization. These typically focus only on optimizing
the aerial image through focus, but may not include sensitivity to mask error as well. These approaches will
be evaluated and discussed. Total CD uniformity is presented as a metric for evaluation of mask solutions.
This includes the impact of dose and focus, but also masks error in estimating the total CD variation of a
contact patterning process. The SRAF solution with the lowest overall variation is the winner. This
methodology is presented for parametric through pitch features, and logic patterns.
The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA
immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical
challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning
technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development
alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling
the pattern spatially through mask design or temporally through innovative processes. These techniques have been
successfully employed for early 32nm node development using 45nm generation tooling. Four different double
patterning techniques were implemented. The first process illustrates local RET optimization through the use of a
split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging
properties and the illumination conditions for each are independently optimized. These regions are then printed
separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that
could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging
with particular focus on both line-end dimension and linewidth control . A double exposure-double etch (DE2)
approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process,
optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that
the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures
with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole
lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay
tolerant . Collectively, the double patterning solutions developed for early learning activities at 32nm can be
extended to 22nm applications.