As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask manufacturers. Techniques including advanced Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the new challenges are continued shrinking Sub-Resolution Assist Features (SRAFs), curvilinear SRAFs, and other complex mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible solutions to these coming challenges. In this paper, we study one such process, characterizing mask manufacturing capability of 10nm and below structures with particular focus on minimum resolution and pattern fidelity.
Demand for mask process correction (MPC) is growing for leading-edge process nodes. MPC was originally intended to
correct CD linearity for narrow assist features difficult to resolve on a photomask without any correction, but it has been
extended to main features as process nodes have been shrinking.
As past papers have observed, MPC shows improvements in photomask fidelity. Using advanced shape and dose
corrections could give more improvements, especially at line-ends and corners. However, there is a dilemma on using
such advanced corrections on full mask level because it increases data volume and run time. In addition, write time on
variable shaped beam (VSB) writers also increases as the number of shots increases.
Optical proximity correction (OPC) care-area defines circuit design locations that require high mask fidelity under mask
writing process variations such as energy fluctuation. It is useful for MPC to switch its correction strategy and permit the
use of advanced mask correction techniques in those local care-areas where they provide maximum wafer benefits. The
use of mask correction techniques tailored to localized post-OPC design can result in similar desired level of data
volume, run time, and write time. ASML Brion and NCS have jointly developed a method to feedforward the care-area
information from Tachyon LMC to NDE-MPC to provide real benefit for improving both mask writing and wafer
This paper explains the detail of OPC care-area feedforwarding to MPC between ASML Brion and NCS, and shows the
results. In addition, improvements on mask and wafer simulations are also shown. The results indicate that the worst
process variation (PV) bands are reduced up to 37% for a 10nm tech node metal case.
As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask
manufacturers. Techniques including advanced optical proximity correction (OPC) and Inverse Lithography
Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the
new challenges are continued shrinking sub-resolution assist features (SRAFs), curvilinear SRAFs, and other complex
mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements
over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature
resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible
solutions to these coming challenges. In this paper, Part 2 of our study, we further characterize an MBMW process for
10nm and below logic node mask manufacturing including advanced pattern analysis and write time demonstration.
Process matching is the ability to precisely reproduce the signature of a given fabrication process while using a different one. A process signature is typically described as systematic CD variation driven by feature geometry as a function of feature size, local density or distance to neighboring structures. The interest of performing process matching is usually to address differences in the mask fabrication process without altering the signature of the mask, which is already validated by OPC models and already used in production. The need for such process matching typically arises from the expansion of the production capacity within the same or different mask fabrication facilities, from the introduction of new, perhaps more advanced, equipment to deliver same process of record masks and/or from the re-alignment of processes which have altered over time. For state-of-the-art logic and memory mask processes, such matching requirements can be well below 2nm and are expected to reduce below 1nm in near future. In this paper, a data preparation solution for process matching is presented and discussed. Instead of adapting the physical process itself, a calibrated model is used to modify the data to be exposed by the source process in order to induce the results to match the one obtained while running the target process. This strategy consists in using the differences among measurements from the source and target processes, in the calibration of a single differential model. In this approach, no information other than the metrology results is required from either process. Experimental results were obtained by matching two different processes at Photronics. The standard deviation between both processes was of 2.4nm. After applying the process matching technique, the average absolute difference between the processes was reduced to 1.0nm with a standard deviation of 1.3nm. The methods used to achieve the result will be described along with implementation considerations, to help assess viability for model driven data solutions to play a role in future, critical mask matching efforts.
With the delay of a next-node lithography solution, lithographers are required to evaluate
double patterning techniques such as double pattern/double etch (DP/DE) to meet scaling
targets for the 22nm logic node. The tightest design rule level to pattern has traditionally
been the first metal level. For this node, target minimum pitches are below 32 nm half
pitch in order to meet cell area requirements. In this paper, we explore implications of
the DP/DE approach when applied to complex 2D metal patterns. In addition to
evaluating stitching rules for line ends, we move into complicated patterning structures
such as landing pads neighboring metal runners and arrays of dense landing pads. These
feature types are critical for area scaling; however, when these structures are patterned in
a DP/DE scheme, the minimum area of the features needed for each pattern layer can be
quite small. In this work, we explore minimum area rules for stitching together patterns
as function of overlap with first pattern, minimum area and proximity to unrelated trench features on the same pattern. These results are shown thru simulation and on the wafer scale using a DP/DE approach which uses current 28 nm node imaging techniques.
Yield of a Variable Shaped Beam (VSB) created photomask is directly related to the quality of the
fracture. The quality of a fracture is determined by three criteria: split CDs, slivers, and fracture
consistency. Split CDs of figures whose widths are under the beam's shot size affect the quality due
to adding an unnecessary shot registration error. Slivers, or extremely skinny shots, are harmful
because they increase write time, adversely affect lithography patterning, and subsequently can
cause inspection errors. Inconsistent fracturing of identical geometry compounds these issues that
Testmask structures devoted to grading the impact of slivers and consistency will be created,
manufactured, and measured to enable statistical analysis of fracture data. These structures will be
systematically designed to cover a wide range of sliver widths and feature geometries. The mean to
target will be evaluated for these test structures, and from this, impact on CD linearity and CD
uniformity can be judged. The effect of slivers on write time will be discussed in a more general
When evaluating the impact of slivers, five criteria should be investigated: sliver length, sliver
width, proximity, avoidability, and location. Each of these criteria either affect lithography or write
Determining how to define the maximum width of a sliver is fracture algorithm dependent, but this
paper gives guidelines that should ease that process. The goal is to fracture identical geometry in an
identical fashion, regardless of orientation or mirroring, while making the shots as large as possible
and avoiding slivers; and when avoiding a sliver is impossible, trying to embed the sliver between
Time-to-mask (ttm) has been growing exponentially in the subwavelength era with the increased application of advanced RET's (Resolution Enhancement Technology). Not only are a greater number of design/mask layers impacted but more-and-more layers also have more severe restrictions on critical dimension uniformity (CDU) despite operating at a very low k1 factors necessitating rigorous but practical tolerancing. Furthermore, designs are also more complex, may be built up from blocks spanning different design styles, and occupy increasingly-large Rayleigh field areas. Given these factors and scales, it's no wonder that the cycle time for verification of a design following RET, is growing however it is doing so exponentially and that this is a critical factor impeding ttm. Until an unambiguously interprable and standard Mask Design Rule (MaskDR) set is created, neither the designer nor the mask supplier can reliably verify manufacturability of the mask for the simple reason that ambiguity and inter-rule conflict are at the source of the problem and that the problem increasingly requires cooperation spanning a large ecosystem of tool, IP, and mask suppliers all needing to essentially speak the same language. Since the 130 nm node, Texas Instruments has enforced a strict set of mask rule checks (MRCs) in their mask data preparation (MDP) flow based on MaskDRs negotiated with their mask suppliers. The purpose of this effort has been to provide an a-priori guarantee that the data shipped to the mask shop can be used to manufacture a mask reliably and with high yield both from a mask standpoint and from the silicon standpoint. As has been reported earlier, mask manufacturing rules are usually determined from assumed or experimentally acquired/validated mask-manufacturing limits. These rules are then applied during RET/MDP data treatment to guide and/or limit pattern correction strategies. With increasing RET and low-k1 lithography challenges, the importance of MRCs compounds. Furthermore, it will be necessary to comprehend certain MRC restrictions in the design flow as well as in the RET and MDP space. While mask tool manufacturers will need to be able specify tools specifications relevant to the MRCs for a particular mask shop flow, software tool suppliers, such as for RET, need to do so as well with tools which comprehend, check for, and enforce MRCs consistently. IDMs, foundaries, mask shops, EDA companies and tool suppliers will need a common language for the discussion on MaskDRs and MRCs in order to reach unambiguous convergence. Experience at Texas Instruments shows that accurate description, specification, and interpretation of MaskDRs and applying the associated MRCs is critical to a successful advanced mask technology strategy. This paper proposes the creation of a standard MaskDR lexicon. The goal of such a lexicon is the standardization of MaskDRs and their definitions such that interested parties from various mask-related disciplines can discuss, negotiate, specify, test and enforce MaskDRs unambiguously. We further propose that this standard be machine readable and directly usable without the necessity for intermediate interpretations. This lexicon would allow the designers, IDMs, foundaries, mask suppliers, and equipment suppliers to unambiguously negotiate and agree upon mask manufacturability requirements for their particular application.
There is a growing realization of the need for highly integrated solutions enabled by new bi-directional data 'pipes' between design and manufacturing. Traditional EDA applications should be able to communicate and collaborate with yield analysis software. Simply adding such capabilities to existing EDA applications is not feasible. Thus, there is a need for an infrastructure that would enable such interaction in a standard way. We call this infrastructure the DFM Platform.
In this article we present new approach to building such a platform. Brief descriptions of potential applications follow the platform architecture. "Via analysis" application includes test chips capabilities, critical area and critical parameter analysis to predict yield for a real design. The "DFM Cell Grading" module applies the concept of DFM to IP Libraries.
Mask manufacturing rules are usually determined from assumed or experimentally acquired mask-manufacturing limits. These rules are then applied during resolution enhancement data treatment to guide and/or limit pattern correction strategies. This technique can be highly reactive and may not allow a careful tradeoff between the mask making capability and the end user needs. We have explored techniques to develop mask manufacturability rules in the context of wafer lithography and device needs.
In this paper, we consider methods to improve the capture and usage of mask making information for resolution enhancement by applying a novel test mask and design, which is tied to a process modeling software. Mask manufacturing models are established from the test maks design and these models are applied to generate geometrical rules and continuous models linking the mask making capability to the lithography requirements. The analysis of mask manufacturing constraints is extended into the device domain through yield prediction tools that capture the impact of lithography variability on device performance.
We find techniques allowing a more dynamic generation of relevant mask making constraints that can optimize both yield and cycle time in the resolution ehancement process flow. Toward this, usage cases are highlighted to illustrate the interaction of specific design layouts and our mask manufacturability.