Proc. SPIE. 5756, Design and Process Integration for Microelectronic Manufacturing III
KEYWORDS: Lithography, Metrology, Data modeling, Process control, Design for manufacturing, Line width roughness, Immersion lithography, Critical dimension metrology, Overlay metrology, Single crystal X-ray diffraction
Immersion lithography at 193nm has emerged as the leading contender for critical patterning through the 32nm technology node. Super-high NA, along with attendant polarization effects, will require re-optimization of virtually every resolution enhancement technology and the implementation of advanced process control at intra-wafer and intra-field levels. Furthermore, interactions of critical dimensions, profiles, roughness, and overlay between layers will impact design margins and become severe yield limiters. In this work, we show how design margins are reduced as a result of hidden process error and how this error can be parsed into unobservable, unsampled, unmodeled, and uncorrectable components. We apply four new process control technologies that use spectroscopic ellipsometry, grating-based overlay metrology, e-beam array imaging, and simulation to reduce hidden systematic error. Feedback of super-accurate process metrics will be critical to the application of conjoint DFM and APC strategies at the 65nm node and beyond. Manufacturing economics will force a trade-off between measurement cost and yield loss that favors greater expenditure on process control.
The goal of SEMATECH Joint Development Project J101 was to accelerate the development of a patterned wafer inspection tool to meet the sensitivity, throughput, and cost requirements for 0.25 micrometers and 0.18 micrometers technology generations. To accomplish this goal, SEMATECH partnered with Tencor Instruments to develop the Tencor Surfscan Advanced Inspection Tool (AIT). This tool is capable of inspecting 100-200 mm wafers with random and repetitive patterns for both particulate contamination and pattern defects. This capability, combined with its high throughput, makes the Surfscan AIT useful as an in-line process monitor. In order to determine its performance on product wafers in a manufacturing environment, a beta version of the AIT system was evaluate at Advanced Micron Devices Fab 25, in Austin, Texas. The evaluation was conducted according to the SEMATECH qualification plan. The final tool development, IRONMAN testing, and beta site evaluation will be described in this paper.
An advanced in-line patterned wafer defect detection system has been developed in a Joint Development Project (JDP) with Tencor Instruments and SEMATECH. The JDP, known as J101, was initiated due to critical needs identified in a SEMATECH Phase 4/5 (0.25 micrometers ) Workshop. The goal of the workshop was to identify the most suitable and cost-effective technology to meet the in-line monitoring needs specified in the National Technology Roadmap for Semiconductors (NTRS), also known as the SIA technology roadmap. This paper will review the inspection requirements identified in the SEMATECH Phase 4/5 (0.25 micrometers ) Workshop, specify the objectives and milestones of the JDP, provide a technology overview of the system, and show results obtained by using the system during alpha and prototype characterization.
A laser scanning system designed for inspection of patterned wafers is described. This system addresses the inspection needs for 64 Mb (0.35 micrometers ) and 256 Mb (0.25 micrometers ) DRAM process technologies. The system is capable of detecting contaminant particles and planar pattern defects on memory and logic devices. The throughput of the system is designed for 30 wafers (200 mm in diameter) per hour. The beam at 488 nm is brought to a focal spot and is scanned on the wafer surface using an acousto-optic deflector (AOD). The entire wafer is scanned under oblique illumination in narrow strips in a serpentine fashion. The specular beam is collected and processed in, what we have named, the autoposition sensor (APS) to servo- lock the height position of the wafer during the scan. The system utilizes multiple independent collection channels positioned around the scan line and it is possible to select the polarization of the collected light for enhanced signal-to-background ratio. The engineering tradeoffs for realizing a system with high throughput and sensitivity are formulated and discussed. Calculations ilustrating scattering from submicron size particles under various polarization conditions are shown. These results lead to optimum design for collection optics. The APS channel is described and illustrated by results indicating that it is possible to keep the surface height of the wafer constant to within 0.4 micrometers in the presence of large changes in topography and wafer reflectivity. Results obtained from a range of production wafers demonstrating detection of 0.1 micrometers anomalies on bare wafer, 0.3 micrometers on memory devices, and 0.4 micrometers on random logic structures are presented.
This paper describes a broad range of design issues that influence the performance of optical equipment for in-line inspection of random (logic) and repetitive (memory) patterns. In particular, we describe the angular distribution of signals from defects on a patterned wafer illuminated by a focused optical beam. We analyze the configuration of both illumination and collection optics to maximize the signal to background ratio for the detection of submicron defects on pattern. In addition, we analyze the distribution of the scattered light as a function of pattern periodicity and orientation with respect to the illuminating beam. The advantages of polarization selection and spatial filtering techniques are explored to enhance the detection sensitivity on repetitive and random pattern wafers. From these results we have developed a new patterned wafer inspection system that offers increased sensitivity and improved defect capture.
Conference Committee Involvement (4)
Metrology, Inspection, and Process Control for Microlithography XXII
25 February 2008 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XXI
26 February 2007 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XX
20 February 2006 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XIX
28 February 2005 | San Jose, California, United States