The NTD (Negative Tone Developer) process has been embraced as a viable alternative to traditionally, more conventional, positive tone develop processes. Advanced technology nodes have necessitated the adopting of NTD processes to achieve such tight design specifications in critical dimensions. Dark field contact layers are prime candidates for NTD processing due to its high imaging contrast. However, reticles used in NTD processes are highly transparent. The transmission rate of those masks can be over 85%. Consequently, lens heating effects result in a non-trivial impact that can limit NTD usability in a high volume mass production environment. At the same time, Source Mask Optimized (SMO) freeform pupils have become popular. This can also result in untoward lens heating effects which are localized in the lens. This can result in a unique drift behavior with each Zernike throughout the exposing of wafers. In this paper, we present our experience and lessons learned from lens heating with NTD processes. The results of this study indicate that lens heating makes impact on drift behavior of each Zernike during exposure while source pupil shape make an impact on the amplitude of Zernike drift. Existing lens models should be finely tuned to establish the correct compensation for drift. Computational modeling for lens heating can be considered as one of these opportunities. Pattern shapes, such as dense and iso pattern, can have different drift behavior during lens heating.
Advanced thermal annealing processes used for transistor enhancing for the state of the art process nodes induce wafer grid deformations. RTA (Rapid Thermal Anneal) and LSA (Laser Scanning Anneal) processes are a few examples. High Order Wafer Alignment (HOWA) method is an effective wafer alignment strategy for wafers with distorted grid signature especially when wafer-to-wafer grid distortion variations are also present. However, usage of HOWA in high volume production environment requires 1) careful initial determination of optimum polynomial order and alignment sampling to be implemented, and 2) matched tool monitoring and controlling strategies and infrastructures to avoid potential HOWA induced drawbacks (i.e. alignment walking).
Higher density on 20nm logic chips require tighter pitches to be implemented not only at critical metal layers, but at BEOL critical VIA layers as well. Smaller pitches on critical via are no longer achievable through the conventional positive tone development (PTD) process. Instead, negative tone development (NTD) is considered, evaluated, and integrated as an alternative, along with the double patterning (DP) method. Additionally, preliminary results on NTD+DP patterning challenges, including patterning verification, are presented in this paper.
The objective of this work was to study the trench and contact hole shrink mechanism in negative tone develop resist processes and its manufacturability challenges associated for 20nm technology nodes and beyond. Process delay from post-exposure to develop, or “queue time”, is studied in detail. The impact of time link delay on resolved critical dimension (CD) is fully characterized for patterned resist and etched geometries as a function of various process changes. In this study, we assembled a detailed, theoretical model and performed experimental work to correlated time link delay to acid diffusion within the resist polymer matrix. Acid diffusion is determined using both a modulation transfer function for diffusion and simple approximation based on Fick’s law of diffusion.