Source-mask optimization (SMO) in optical lithography has in recent years been the subject of increased
exploration as an enabler of 22/20nm and beyond technology nodes [1-6]. It has been shown that intensive
optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive
solutions in both the source and mask, which yields improved lithographic performance. This paper
will demonstrate the value of SMO software in resolution enhancement techniques (RETs). Major benefits
of SMO include improved through-pitch performance, the possibility of avoiding double exposure, and
superior performance on two dimensional (2D) features. The benefits from only optimized source, only
optimized mask, and both source and mask optimized together will be demonstrated. Furthermore, we
leverage the benefits from intensively optimized masks to solve large array problems in memory use models
(MUMs). Mask synthesis and data prep flows were developed to incorporate the usage of SMO, including
both RETs and MUMs, in several critical layers during 22/20nm technology node development.
Experimental assessment will be presented to demonstrate the benefits achieved by using SMO during
22/20nm node development.
The 20nm node, with a targeted wiring pitch of 64nm, is the first technology node to dip below the fundamental k1=0.25
resolution limit of high-NA 193nm immersion lithography. Double-patterning has been applied in previous technology
nodes to address specific image quality issues such as line-end shortening or poor process window on contacts and vias,
but never before has double-patterning been used to form images below the frequency-doubled resolution-limit of optical
lithography. This paper describes the design-technology
co-optimization efforts exercised by the alliance program for
Bulk CMOS technology development at IBM in pursuit of cost-effective double-patterning for the 20nm technology
node. The two primary double-patterning contenders, pitch-splitting and sidewall-image-transfer, are reviewed and their
unique layout decomposition requirements are contrasted. Double-patterning design enablement solutions and their
particular applicability to each step in the design flow are described. The paper closes with a review of the costeffectiveness
of current double-patterning solutions, highlighting the important role of design-technology cooptimization in ensuring continued cost-effective semiconductor scaling.
Improvements in resolution of exposure systems have not kept pace with increasing density of semiconductor products. In order to keep shrinking circuits using equipment with the same basic resolution, lithographers have turned to options such as double-patterning, and have moved beyond model-based OPC in the search for optimal mask patterns. Inverse Lithography Technology (ILT) is becoming one of the strong candidates in 32nm and below single patterning, low-k1 lithography regime. It enables computation of optimum mask patterns to minimize deviations of images from their targets not only at nominal but also over a range of process variations, such as dose, defocus, and mask CD errors. When optimizing for a factor, such as process window, more complex mask patterns are often necessary to achieve the desired depth of focus. Complex mask patterns require more shots when written with VSB systems, increasing the component of mask cost associated with writing time. It can also be more difficult to inspect or repair certain types of complex patterns. Inspection and repair may take more time, or require more expensive equipment compared to the case with simpler masks. For these reasons, we desire to determine the simplest mask patterns that meet necessary lithographic manufacturing objectives. Luminescent ILT provides means to constrain complexity of mask solutions, each of which is optimized to meet lithographic objectives within the bounds of the constraints. Results presented here show trade-offs to process window performance with varying degrees of mask complexity. The paper details ILT mask simplification schemes on contact arrays and random logic, comparing process window trade-offs in each case. Ultimately this method enables litho and mask engineers balance lithographic requirements with mask manufacturing complexity and related cost.
A Pixel-based sub-resolution assist feature (SRAF) insertion technique has been considered as one of the promising
solutions by maximizing the common process window. However, process window improvement of the pixel-based
SRAF technique is limited by the simplification of SRAFs for mask manufacturability. Mask simplification and mask
rule check (MRC) constraints parameters for pixel-based SRAF technique are the critical factors for mask production
without a big loss of its benefit. In this study, correlation of MRC control was analyzed in terms of the robustness to
process variation for a contact layer of 32nm device node. An optimum condition of MRC constraints was selected by
balancing the process window and mask manufacturability. In addition, a novel and practical methodology for 32nm
device node development was proposed to keep the mask complexity low and to take full advantage of process window
improvement using pixel-base SRAF insertion.
If RET selection by simulation is to be successful for the deep sub-wavelength technologies
of today, then the predictions of the simulator must be quantitatively accurate over the parameter
space of interest. The Rigorous Physical resist Model (RPM) within PROLITH and Lithoware is
separable from the illumination conditions and the reflection behavior of the wafer stack, and thus
should be an excellent candidate for such projects.
In this work, the RPM is calibrated for a commercially available ArF photoresist using topdown
CD-SEM data, including focus-exposure matrices and CD vs. mask pitch data, under fixed
process conditions. It will be shown that this RPM is able to predict the performance of line, trench
and contact features, with quantitative accuracy, under different numerical aperture and illumination
conditions, even when the wafer stack is altered significantly. The stack alterations include resist
thickness change, the presence or absence of an immersion topcoat, substitution of different
underlying substrate materials and the use of a single or double layer anti-reflection coating. The
resist model accurately describes both the experimental calibration data and two separate
experimental validation datasets. The RMS error seen in the extrapolative predictions is comparable
to that observed between the model and the original calibration dataset.
Sub-resolution assist features (SRAFs) have been used to enhance lithographic process window of main features. As the device is scaled down, the SRAF size decreases drastically and the distance between main features and SRAF closes up. The variation of main feature CD and SRAF size from mask production process influences destructively on gate CD control and it makes the device performance degraded. Fabrication of small and uniform-sized SRAFs is one of the key mask technologies because mean-to-target (MTT) and CD uniformity of SRAFs are more difficult to be controlled than those of main features. In addition, for sub-50 nm design nodes, mask topography effects can not be neglected because exposure wavelength is similar to a mask pitch from main feature to SRAF or SRAF to SRAF. In order to consider mask topography effects, all lithographic simulations were performed with a rigorous coupled wave analysis (RCWA) electromagnetic field calculation.
In this study, we will demonstrate that SRAF size tolerance is deduced from the effects of SRAF size deviation from the mask production on a main feature CD. To define the SRAF size deviation effects, main feature CD variation is simulated for different SRAF sizes. We will explore SRAF size tolerances for sub-50 nm design nodes. It can be suggested as one of the mask requirements.