Design weak points that have narrow process window and limits wafer yield, or hotspots, continue to be a major issue in semiconductor photolithography. Resolution enhancement techniques (RET) such as advanced optical proximity correction (OPC) techniques and source mask optimization (SMO) are employed to mitigate these issues. During yield ramp for a given technology node, full-chip lithography simulation, pattern-matching and machine learning are adopted to detect and remedy the weak points from the original design , . This is typically an iterative process by which these points are identified in short-loop lithography testing. Design retarget and/or OPC modifications are made to enhance process window until the yield goal is met. This is a high cost and time consuming process that results in a slow yield ramp for existing production nodes and increased time to market (TTM) for new node introduction. Local hotspot correction through mask and wafer harmonization is a method to enhance wafer yield with low cost and short cycle time compared to the iterative method. In this paper, a fast and low cost approach to hotspot correction is introduced. Hotspots were detected on wafer after OPC and characterized by using advanced mask characterization and optimization (AMCO) techniques. Lithographic simulations and AIMS measurement were used to verify the hotspot correction method. Finally, the validity of this new approach was evaluated by process window analysis and circuit probe yield test at wafer.
A new technology transforms mask inspection images through focus into 3D lithography images in resist. This enables early detection and ranking of hotspots, and distinguishes mask-induced and process-induced hotspots. The results can be used in several ways including: 1) feed back to OPC teams to improve process window; 2) feed forward to the litho team for scanner adjustment; and, 3) feed forward to wafer inspection in the form of care areas to reduce time to result for wafer-based process window discovery.