KEYWORDS: Clocks, Field programmable gate arrays, Control systems, Computer simulations, Feature extraction, Microelectronics, Very large scale integration, Signal generators, Multiplexers, Computer architecture
The non-stop advance of computer architectures and their wide variety, not only in types (pipeline, super pipeline, etc.) but also in application fields, as well as their high cost from conception to the implementation, make it necessary to have tools that, on the one hand, help to design and to evaluate processors comfortably, and, on the other, link up with commercial design flows of microelectronics circuits (in FPGA technologies or VLSI Deep-submicron).
This work presents HEAPAN, a tool for the high level design and evaluation of processors. The main idea of this tool is to be able to describe a processor at high level easily and cheaply in order to compare different architectural options. Behavioural verifications are done at RT level, with descriptions automatically generated by HEAPAN.
For the development of HEAPAN, a study of the most important distinctive features of major recent commercial processors has been carried out, and the most relevant blocks that make up these architectures have been extracted. These blocks have been implemented as functional units of the tool. In this way the construction of a processor with HEAPAN basically consists of selecting and interconnecting those blocks. Finally the validity of the developed tool has been tested through the design of a simple processor, verifying its behaviour and implementing it in a deep-submicron technology.
The availability of higher performance (in area, time and power consumption) and greater precision binary adders is a
constant requirement in digital systems. Consequently, the design and characterization of adders and, most of all, their
adaptation to the requisites of present-day deep-submicron technologies, are today still issues of concern. The binary
adder structures in deep-submicron technologies must be revised to achieve the best balance between the number of bits in
the adder and its delay, area and power consumption. It is therefore very important to make an effort to carefully optimize
adder structures, thus obtaining improvements in digital systems. This communication presents the optimization of adder
structures for implementations in deep-submicron technologies through their partitioning into blocks. This partitioning
consists of dividing the number of input bits to the adder into several subsets of bits that will constitute the inputs to
several adder structures of the same or of different types. The structures used to accomplish this study range from the
more traditional types, such as the carry look ahead adder, the ripple carry adder or the carry select adder, to more
innovative kinds, like the parallel prefix adders of the type proposed by Brent-Kung, Han-Carlson, Kogge-Stone or
Ladner-Fischer. The analyses carried out allow the characterization of structures implemented in deep-submicron
technologies for area, delay and power consumption parameters.
Integration technologies have favored the design and implementation of more complex circuits. Thanks to this increased complexity, these circuits are capable of implementing algorithms which a few years ago were too expensive in both area and computational resources. However, they now offer interesting choices which should be considered.
This new generation of integrated circuits nevertheless presents other kinds of restrictions that the designer should bear in mind. Parameters such as frequency of operation or power consumption are new restrictions that the designer has to deal with in order to fulfill the conditions established by the circuit functionality.
Finally, the shrinking integration scale of current technologies makes the timing behavior of the design differ from previous technologies. Thus, a review of the timing behavior of the digital circuit should be done. So far, arithmetic circuits have been used as a benchmark for the analysis and design procedures of digital circuits. Therefore, it is our goal now to analyze both conventional and modern arithmetic circuits structures for different deep-submicron technologies.
To achieve this goal, a good solution is to characterize a set of algorithmic circuits for several deep submicron processes, so that the designer can select the most suitable one depending upon the intended application and existing restrictions.
In this paper, the first steps to attain such selection are presented. In particular, we propose a design and VHDL characterization methodology based on an RTL description of each component, on the utilization of an automated synthesis tool, and on the generation of logic characteristics from the logic level. This methodology is applied to a set of adders structures, the results of which are also presented.