PROCEEDINGS ARTICLE | May 23, 2007
Proc. SPIE. 6590, VLSI Circuits and Systems III
KEYWORDS: Clocks, Field programmable gate arrays, Control systems, Computer simulations, Feature extraction, Microelectronics, Very large scale integration, Signal generators, Multiplexers, Computer architecture
The non-stop advance of computer architectures and their wide variety, not only in types (pipeline, super pipeline, etc.) but also in application fields, as well as their high cost from conception to the implementation, make it necessary to have tools that, on the one hand, help to design and to evaluate processors comfortably, and, on the other, link up with commercial design flows of microelectronics circuits (in FPGA technologies or VLSI Deep-submicron).
This work presents HEAPAN, a tool for the high level design and evaluation of processors. The main idea of this tool is to be able to describe a processor at high level easily and cheaply in order to compare different architectural options. Behavioural verifications are done at RT level, with descriptions automatically generated by HEAPAN.
For the development of HEAPAN, a study of the most important distinctive features of major recent commercial processors has been carried out, and the most relevant blocks that make up these architectures have been extracted. These blocks have been implemented as functional units of the tool. In this way the construction of a processor with HEAPAN basically consists of selecting and interconnecting those blocks. Finally the validity of the developed tool has been tested through the design of a simple processor, verifying its behaviour and implementing it in a deep-submicron technology.
