Hybrid metrology (HM) is the practice of combining measurements from multiple toolset types in order to enable or improve metrology for advanced structures. HM is implemented in two phases: Phase-1 includes readiness of the infrastructure to transfer processed data from the first toolset to the second. Phase-2 infrastructure allows simultaneous transfer and optimization of raw data between toolsets such as spectra, images, traces – co-optimization. We discuss the extension of Phase-1 to include direct high-bandwidth communication between toolsets using a hybrid server, enabling seamless fab deployment and further laying the groundwork for Phase-2 high volume manufacturing (HVM) implementation. An example of the communication protocol shows the information that can be used by the hybrid server, differentiating its capabilities from that of a host-based approach. We demonstrate qualification and production implementation of the hybrid server approach using CD-SEM and OCD toolsets for complex 20nm and 14nm applications. Finally we discuss the roadmap for Phase-2 HM implementation through use of the hybrid server.
Until now, metrologists had no statistics-based method to determine the sampling needed for an experiment before the start that accuracy experiment. We show a solution to this problem called inverse total measurement uncertainty (TMU) analysis, by presenting statistically based equations that allow the user to estimate the needed sampling after providing appropriate inputs, allowing him to make important “risk versus reward” sampling, cost, and equipment decisions. Application examples using experimental data from scatterometry and critical dimension scanning electron microscope tools are used first to demonstrate how the inverse TMU analysis methodology can be used to make intelligent sampling decisions and then to reveal why low sampling can lead to unstable and misleading results. One model is developed that can help experimenters minimize sampling costs. A second cost model reveals the inadequacy of some current sampling practices—and the enormous costs associated with sampling that provides reasonable levels of certainty in the result. We introduce the strategies on how to manage and mitigate these costs and begin the discussion on how fabs are able to manufacture devices using minimal reference sampling when qualifying metrology steps. Finally, the relationship between inverse TMU analysis and hybrid metrology is explored.
Work using the concept of a co-optimization-based metrology hybridization is presented. Hybrid co-optimization involves the combination of data from two or more metrology tools such that the output of each tool is improved by the output of the other tool. Here, the image analysis parameters from a critical dimension scanning electron microscope (CD-SEM) are modulated by the profile information from optical critical dimension (OCD, or scatterometry), while the OCD-extracted profile is concurrently optimized through addition of the CD-SEM CD results. The test vehicle utilized is the 14-nm technology node-based FinFET high-k/interfacial layer (HK/IL) structure. When compared with the nonhybrid approach, the correlation to reference measurements of the HK layer thickness measurement using hybrid co-optimization resulted in an improvement in relative accuracy of about 40% and in R2 from 0.81 to 0.91. The measurement of the IL thickness also shows an improvement with hybrid co-optimization: better matching to the expected conditions as well as data that contain less noise.
At 1× node, a three-dimensional (3-D) FinFET process raises a number of new metrology challenges for process control, including gate height and fin height. At present, there is a metrology gap in inline in-die measurement of these parameters. To fill this metrology gap, in-column beam tilt has been implemented on Applied Materials V4i+ critical dimension scanning electron microscope for height measurement. Low-tilt (5 deg) and high-tilt (14 deg) beam angles have been calibrated to obtain the height and the sidewall angle information. Evaluation of its feasibility and production worthiness is done with applications in both gate height and fin height measurements. Transmission electron microscope correlation with an R2 equal to 0.89 and a precision of 0.81 nm have been achieved on various in-die features in a gate height application. The initial fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to greater challenges brought by the fin profile, yet it is promising for the first attempt. Sensitivity to design of experiment offset die-to-die and in-die variations is demonstrated in both gate height and fin height. The process defect is successfully captured with inline gate height measurement. This is the first successful demonstration of inline in-die gate height measurement for a 14-nm FinFET process control.
At 1X node, 3D FinFETS raise a number of new metrology challenges. Gate height and fin height are two of the most important parameters for process control. At present there is a metrology gap in inline in-die measurement of these parameters. In order to fill this metrology gap, in-column beam tilt has been developed and implemented on Applied Materials V4i+ top-down CD-SEM for height measurement. A low tilt (5°) beam and a high tilt (14°) beam have been calibrated to obtain two sets of images providing measurement of sidewall edge width to calculate height in the host. Evaluations are done with applications in both gate height and fin height. TEM correlation with R<sup>2</sup> being 0.89 and precision of 0.81nm have been achieved on various in-die features in gate height application. Fin height measurement shows less accuracy (R<sup>2</sup> being 0.77) and precision (1.49 nm) due to challenges brought by fin geometry, yet still promising as first attempt. Sensitivity to DOE offset, die-to-die and in-die variation is demonstrated in both gate height and fin height. Process defect is successfully captured from inline wafers with gate height measurement implemented in production. This is the first successful demonstration of inline in-die gate height measurement for 14nm FinFET process control.
When designing an experiment to assess the accuracy of a tool as compared to a reference tool, semiconductor metrologists are often confronted with the situation that they must decide on the sampling strategy before the measurements begin. This decision is usually based largely on the previous experience of the metrologist and the available resources, and not on the statistics that are needed to achieve acceptable confidence limits on the final result. This paper shows a solution to this problem, called inverse TMU analysis, by presenting statistically-based equations that allow the user to estimate the needed sampling after providing appropriate inputs, allowing him to make important “risk vs. reward” sampling, cost, and equipment decisions. Application examples using experimental data from scatterometry and critical dimension scanning electron microscope (CD-SEM) tools are used first to demonstrate how the inverse TMU analysis methodology can be used to make intelligent sampling decisions before the start of the experiment, and then to reveal why low sampling can lead to unstable and misleading results. A model is developed that can help an experimenter minimize the costs associated both with increased sampling and with making wrong decisions caused by insufficient sampling. A second cost model is described that reveals the inadequacy of current TEM (Transmission Electron Microscopy) sampling practices and the enormous costs associated with TEM sampling that is needed to provide reasonable levels of certainty in the result. These high costs reach into the tens of millions of dollars for TEM reference metrology as the measurement error budgets reach angstrom levels. The paper concludes with strategies on how to manage and mitigate these costs.
In recent years Hybrid Metrology has emerged as an option for enhancing the performance of existing measurement toolsets and is currently implemented in production<sup>1</sup>. Hybrid Metrology is the practice to combine measurements from multiple toolset types in order to enable or improve the measurement of one or more critical parameters. While all applications tried before were improved through standard (sequential) hybridization of data from one toolset to another, advances in device architecture, materials and processes made possible to find one case that demanded a much deeper understanding of the physical basis of measurements and simultaneous optimization of data. This paper presents the first such work using the concept of co-optimization based hybridization, where image analysis parameters of CD-SEM (critical dimensions Scanning Electron Microscope) are modulated by profile information from OCD (optical critical dimension – scatterometry) while the OCD extracted profile is concurrently optimized through addition of the CD-SEM CD results. Test vehicle utilized in this work is the 14nm technology node based FinFET High-k/Interfacial layer structure.