NXE:3300B scanners have been operational at customer sites since almost two years, and the NXE:3350B, the 4th generation EUV system, has started shipping at the end of 2015. All these exposure tools operate using MOPA pre-pulse source technology, which enabled significant productivity scaling, demonstrated at customers and at ASML. Having achieved the required throughput to support device development, the main priority of the ASML EUV program has shifted towards improving stability and availability. Continuous progresses in defectivity reduction and in the realization of a reticle pellicle are taking place at increased speed. Today’s overlay and imaging results are in line with the requirements of 7nm logic devices; Matched Machine overlay to ArF immersion below 2.5 nm and full wafer CDU performance of less than 1.0nm are regularly achieved. The realization of an intensity loss-less illuminator and improvements in resist formulation are significant progress towards enabling the use of EUV technology for 5nm logic devices at full productivity. This paper will present an overview of the status of the ASML EUV program and product roadmap by reviewing the current performance and on-going developments in productivity, imaging, overlay and mask defectivity reduction.
Towards the end of 2014, ASML committed to provide a EUV pellicle solution to the industry. Last year, during SPIE Microlithography 2015, we introduced the NXE pellicle concept, a removable pellicle solution that is compatible with current and future patterned mask inspection methods. This paper shows results of how we took this concept to a complete EUV pellicle solution for the industry. We will highlight some technical design challenges we faced developing the NXE pellicle and how we solved them. We will also present imaging results of pellicle exposures on a 0.33 NA NXE scanner system. In conjunction with the NXE pellicle, we will also present the supporting tooling we have developed to enable pellicle use.
Multiple NXE:3300 are operational at customer sites. These systems, equipped with a Numerical Aperture (NA) of 0.33, are being used by semiconductor manufacturers to support device development. Full Wafer Critical Dimension Uniformity (CDU) of 1.0 nm for 16nm dense lines and 1.1 nm for 20nm isolated space and stable matched overlay performance with ArF immersion scanner of less than 4nm provide the required lithographic performance for these device development activities. Steady progresses in source power have been achieved in the last 12 months, with 100Watts (W) EUV power capability demonstrated on multiple machines. Power levels up to 90W have been achieved on a customer machine, while 110W capability has been demonstrated in the ASML factory. Most NXE:3300 installed at customers have demonstrated the capability to expose 500 wafers per day, and one field system upgraded to the 80W configuration has proven capable of exposing 1,000 wafers per day. Scanner defectivity keeps being reduced by a 10x factor each year, while the first exposures obtained with full size EUV pellicles show no appreciable difference in CDU when compared to exposures done without pellicle. The 4<sup>th</sup> generation EUV system, the NXE: 3350, is being qualified in the ASML factory.
As EUV approaches high volume manufacturing, reticle defectivity becomes an even more relevant topic for further investigation. Current baseline strategy for EUV defectivity management is to design, build and maintain a clean system without pellicle. In order to secure reticle front side particle adders to an acceptable level for high volume manufacturing, EUV pellicle is being actively investigated. Last year ASML reported on our initial EUV pellicle feasibility. In this paper, we will update on our progress since then. We will also provide an update to pellicle requirements published last year. Further, we present experimental results showing the viability and challenges of potential EUV pellicle materials, including, material properties, imaging capability, scalability and manufacturability.
Through collaborative efforts ASML and TEL are continuously improving the process performance for the
LITHIUS Pro <i>-i/</i> TWINSCAN XT:1900Gi litho cluster. In previous work from this collaboration, TEL and ASML
have investigated the CDU and defectivity performance for the 45nm node with high through put processing.
CDU performance for both memory and logic illumination conditions were shown to be on target for ITRS roadmap
specifications. Additionally, it was shown that the current defect metrology is able to measure the required defect size
of 30nm with a 90% capture rate. For the target through put of 180wph, no added impact to defectivity was seen from
the multi-module processing on the LITHIUS Pro <i>-i</i>, using a topcoat resist process. For increased productivity, a new
bevel cut strategy was investigated and shown to have no adverse impact while increasing the usable wafer surface.
However, with the necessity of double patterning for at least the next technology node, more stringent requirements are
necessary to prevent, in the worst case, doubling of the critical dimension variation and defectivity.
In this work, improvements in process performance with regards to critical dimension uniformity and defectivity are
investigated to increase the customer's productivity and yield for whichever double patterning scheme is utilized.
Specifically, TEL has designed, evaluated and proven the capability of the latest technology hardware for post exposure
bake and defect reduction. For the new post exposure bake hardware, process capability data was collected for 40nm
CD targets. For defectivity reduction, a novel concept in rinse technology and processing was investigated on
hydrophobic non top coat resists processes. Additionally, improvements to reduce micro bridging were evaluated.
Finally bevel rinse hardware to prevent contamination of the immersion scanner was tested.
In order to prepare for the next generation technology manufacturing, ASML and TEL are investigating the process
manufacturability performance of the CLEAN TRACK<sup>TM</sup> LITHIUS Pro<sup>TM</sup>-<i>i</i>/ TWINSCAN<sup>TM</sup> XT:1900Gi lithocluster at
the 45nm node. Previous work from this collaboration showed the feasibility of 45nm processing using the LITHIUS<sup>TM</sup>
<i>i</i>+/TWINSCAN XT:1700i. <sup>1</sup> In this work, process performance with regards to critical dimension uniformity and
defectivity are investigated to determine the robustness for manufacturing of the litho cluster. Specifically, at the spinner
and PEB plate configuration necessary for the high volume manufacturing requirement of 180 wafers per hour, process
data is evaluated to confirm the multi-module flows can achieve the required process performance. Additionally, an
improvement in the edge cut strategy necessary to maximize the usable wafer surface without negative impact to defectivity is investigated.