Collaborative hardening and hardware redundancy are nowadays the most interesting solutions in terms of fault tolerance achieved and low extra cost imposed to the project budget. Thanks to the powerful and cheap digital devices that are available in the market, extra processing capabilities can be used for redundant tasks, not only in early data processing (sensed data) but also in routing and interfacing1
Steganalysis is a process to detect hidden data in cover documents, like digital images, videos, audio files, etc. This is the inverse process of steganography, which is the used method to hide secret messages. The widely use of computers and network technologies make digital files very easy-to-use means for storing secret data or transmitting secret messages through the Internet. Depending on the cover medium used to embed the data, there are different steganalysis methods. In case of images, many of the steganalysis and steganographic methods are focused on JPEG image formats, since JPEG is one of the most common formats. One of the main important handicaps of steganalysis methods is the processing speed, since it is usually necessary to process huge amount of data or it can be necessary to process the on-going internet traffic in real-time. In this paper, a JPEG steganalysis system is implemented in an FPGA in order to speed-up the detection process with respect to software-based implementations and to increase the throughput. In particular, the implemented method is the JPEG-compatibility detection algorithm that is based on the fact that when a JPEG image is modified, the resulting image is incompatible with the JPEG compression process.
Current circuit complexity requires faster fault injection techniques to allow the evaluation of a high number of faults in
a reasonable time. In particular, FPGA emulation has proven to be a performance effective method to analyze the
behavior of digital circuits in the presence of soft errors due to SEU effects. In general, fault emulation-based solutions
that use circuit instrumentation to inject faults in the literature does not consider the fault emulation in circuits with
embedded memories. The few existing proposals that study this kind of circuits are oriented to inject faults in
microprocessors, are slow solutions with respect to the injection in flip-flops and with a poor capacity to analyze the
circuit behavior, due to the limited accessibility in memories (a word memory per clock cycle). Embedded memories are
more and more usual and large in modern designs, and therefore, the emulation of the embedded memories is a problem
of rising importance. The proposed models presented in this work allow the fault emulation in embedded memories,
injection faults and observing their effects in a fast way.
KEYWORDS: Electronics, Digital signal processing, Data modeling, Field programmable gate arrays, Control systems, Analog electronics, Digital electronic circuits, Digital electronics, Prototyping, Device simulation
In the design of Power Electronics converters, several approaches can be chosen for the implementation of the closed
loop control. The use of a digital control loop implemented in a FPGA is becoming quite common. For the design of
such a system, a simulation environment must be provided to check the digital and analog part working together. The
simulation of both the analog and digital part is a very difficult task, which involves the simultaneous usage of an analog
and a digital simulator, or the use of a mixed signal simulator. In this paper, we present a method to perform mixed
signal simulation. The simulation is performed by linking PSIM analog simulator and ModelSim digital simulator. This
method has proven to be very effective in the design of digital control circuits for power converters, implemented in
Fault Tolerance has become an important requirement for integrated circuits, not only in safety critical applications like aerospace circuits, but also for applications working at the earth surface. Since the appearance of nanometer technologies, the sensitiveness of integrated circuits to radiation has increased notably, making the occurrence of soft errors much more frequent. Therefore, hardened circuits are currently required in many applications where fault tolerance was not a requirement in the very near past. In this paper, tools and methods for the whole hardening process of a circuit are presented: tools for the automatic insertion of fault tolerant structures in a circuit description and methods for the evaluation of fault tolerance achieved. These methods allow the evaluation of fault tolerance by means of emulation in platform FPGAs, which offer a much faster way to perform evaluation than simulation based techniques. Different circuits are used to test the proposed tool for inserting fault tolerant structures. Fault tolerance evaluation is performed using the proposed fault emulation methods, before and after applying hardening process, showing the fault tolerance improvement. The proposed techniques for evaluation have been compared, in terms of evaluation time, with previously proposed solutions and with simulation based solutions, showing improvements of several orders of magnitude.
This work presents a prototype low pass continuous time sigma delta modulator which uses transmission lines in its loop filter rather than capacitive integrators. As has been shown in prior theoretical work, such a structure allows to desensitize the modulator against clock jitter and excess loop delay. The parameters of the analog components of this design are independent of the sampling clock, as long as the clock frequency has to fit only with the length of the external transmission lines. The prototype single-bit modulator was designed for an oversampling ratio of 128. When the modulator is clocked at 53.7MHz achieves a peak SNR of 67 dB. In an experiment with an excessive clock jitter of 1% of the clock period and a test tone of -10dBfs is applied, the SNDR is degraded by only 5dB compared to the case without jitter.
Functional validation plays an important role in the design cycle of digital integrated circuits. The generation of good test benches is required for checking the complete circuit behaviour. Early location of design errors could highly reduce the development time and cost for these circuits. There are several initiatives for the development of methods that enhance the functional validation of a design. Traditionally, logic abstraction level has been most employed for this purpose, but recent years have shown a strong trend to treat the problem at higher abstraction levels, where design teams normally work. High abstraction levels and automatic synthesis tools are currently being used in top-down methodology. These aspects make difficult to find out design errors when the circuit is described in lower levels of abstraction. It is crucial to obtain a complete functional validation system applicable in the first design stages, where circuits are currently being designed, and also usable along the whole design process for further test plans.
In this paper we propose a complete methodology for performing high quality functional validation. The proposed method checks the capability of a given test bench to detect design errors in a circuit description. This checking employs functional simulation of the circuit description at RT level together with the application of error models. An automatic and formal protocol has been developed so that design teams could apply it with no extra effort. The method provides a measurement of the quality of functional validation as well as the location of non-enough validated areas in the circuit.
Therefore, the proposed method helps designers in the process of performing the functional validation of their circuits, which could be applied automatically from RT descriptions to lower abstraction levels. Finally, experimental results have proved the correctness of the proposed method as well as the error models applied.