According to the ITRS roadmap, semiconductor industry drives the 193nm lithography to its limits, using techniques like Double Pattern Technology (DPT), Source Mask Optimization (SMO) and Inverse Lithography Technology (ILT). In terms of considering the photomask metrology, full in-die measurement capability is required for registration and overlay control with challenging specifications for repeatability and accuracy. <p> </p>Double patterning using 193nm immersion lithography has been adapted as the solution to enable 14nm technology nodes. The overlay control is one of the key figures for the successful realization of this technology. In addition to the various error contributions from the wafer scanner, the reticles play an important role in terms of considering lithographic process contributed errors. Accurate pattern placement of the features on reticles with a registration error below 4nm is mandatory to keep overall photomask contributions to overlay of sub 20nm logic within the allowed error budget.<p> </p> In this paper, we show in-die registration errors using 14nm DPT product masks, by measuring in-die overlay patterns comparing with regular registration patterns. The mask measurements are used to obtain an accurate model to predict mask contribution on wafer overlay of double patterning technology.
In the High NA process, pattern environment will become very aggressive because of scattering effect. Especially on metal layers, maybe it will cause pattern bridge when the pattern density is varied. We need to find out the root cause and have a good solution to minimize the wafer CD difference that comes from environmental effect (pattern density). In this paper, we analyze the root cause by checking the pattern density influence on mask CD and wafer printing CD. We design different pattern density layout to measure the mask CD error, use AIMS (Aerial Image Measurement System) to measure the aerial image CD and print wafer to check the real result. Then, we try to add some assistant feature (pattern density balance) and use simulation tool to simulate whether this method can have improvement.
Influence of the mask error becomes serious because of the shrinkage of device pitch. The impact of mask line width
roughness (LWR) on wafer CD needs to be studied on advanced node, because the device performance of semiconductor
will be impacted seriously by wafer LWR/LER (line edge roughness). The Gate line width variation is a critical issue on
In this paper, we evaluate the LWR relationship between mask and wafer. We start the mask and wafer LWR study by
simulation (aerial image model, and resist model) to see whether simulation meets optical theory. Besides, we also
confirm the wafer printing result to compare simulation and wafer performance. Based on our study, simulation and
wafer data show that the mask LWR has no obvious impact on wafer LWR even if on EUV (13.5nm wavelength)
Two aspects are critical when a new reticle type is introduced in a wafer fab: printability and reticle
inspection. In this study, we inspected 4 PSM reticles at the 45nm technology node, at P90, on the 5xx
TeraScanHR platform. We successfully inspected SL2+ reticles of the PSM type at P90. We forecast
that in a high volume 32nm node production environment, P72 SL2+ will address the inspectability
challenges associated with PSM masks. This is based on strict requirements for sensitivity on
contamination defects, inspectability, and cost of ownership, as when UMC addressed their wafer