Improving Critical Dimension Uniformity (CDU) for spacer double patterning features is a high priority for double
patterning technology. In spacer double patterning the gaps between the spacers are established through various
processes (litho, etch, deposition) with different process fingerprints and the CDU improvement of these gaps requires an
improved control solution. Such a control solution is built upon two pillars: metrology and a control strategy.
In this paper Spacer Patterning Technology CDU control using an angle resolved scatterometry tool is evaluated. CD
results obtained with this scatterometer on CDU wafers are measured and the results are correlated with those from the
traditional CD-SEM. CD wafer fingerprints are compared before and after applying the advanced control strategy and
CDU improvements are reported. Based on the results it is concluded that scatterometry qualifies for a spacer process
CDU control loop in a manufacturing environment.
Typical overlay metrology marks like Box-in-Box or Advanced-Imaging-Marks print surprisingly poor when exposed
with extreme off-axis-illumination. This paper analyzes the root-cause for this behavior and establishes a method how to
understand and predict the results of overlay metrology on resist. A simulation flow is presented which covers the
lithographic exposure as well as the actual inspection of the resist profiles. This flow is then used to study the impact of
scanner/process imperfections on the overlay measurements; both image-based and diffraction-based overlay metrology
are covered. This helps to gain a deeper understanding of the critical parameters in the printing and inspection of overlay
marks, and eventually develop and assess mark enhancement strategies for image-based overlay metrology such as
chopping, or assess the benefit of diffraction-based overlay metrology. In parallel to the simulations, results of wafer
exposures are presented which investigate various aspects of overlay metrology and validate our simulations.
Overlay performance will be increasingly important for Spacer Patterning Technology (SPT) and Double Patterning
Technology (DPT) as various Resolution Enhancement Techniques are employed to extend the resolution limits of
lithography. Continuous shrinkage of devices makes overlay accuracy one of the most critical issues while overlay
performance is completely dependent on exposure tool.
Image Based Overlay (IBO) has been used as the mainstream metrology for overlay by the main memory IC companies,
but IBO is not suitable for some critical layers due to the poor Tool Induced Shift (TIS) values. Hence new overlay
metrology is required to improve the overlay measurement accuracy. Diffraction Based Overlay (DBO) is regarded to
be an alternative metrology to IBO for more accurate measurements and reduction of reading errors. Good overlay
performances of DBO have been reported in many articles. However applying DBO for SPT and DPT layers poses
extra challenges for target design. New vernier designs are considered for different DPT and SPT schemes to meet
overlay target in DBO system.
In this paper, we optimize the design of the DBO target and the performance of DBO to meet the overlay specification
of sub-3x nm devices which are using SPT and DPT processes. We show that the appropriate vernier design yields
excellent overlay performance in residual and TIS. The paper also demonstrated the effects of vernier structure on
overlay accuracy from SEM analysis.
Current image based overlay metrology accuracy will not be suitable for the critical layers of near future memory
production. At current nodes, measurement reproducibility of 0.6nm or better is required. The number of sampling points
is also expected to increase due to the need for higher order process corrections on the exposure tool. To maintain or
improve total measurement cost, these requirements should be met without negatively impacting throughput.
In this paper we will study a novel, diffraction-based system especially designed to meet these challenging requirements
for next generation memory devices. In addition to overlay metrology, the system is capable of measuring CD and side
wall angle (SWA) within the same measurement cycle. The system can also be used to monitor exposure tool overlay
and focus stability. In this paper we intend to examine the metrics used to evaluate the overlay metrology performance
critical for a DRAM production environment. We also intend to spend much of the paper taking a deeper look at how we
can combine the overlay and CD metrology functionalities to examine the asymmetric profile of target gratings.
One of the critical applications for diffraction based overlay metrology is in understanding the asymmetric properties of
target gratings across a wafer. Reconstructing asymmetric profiles quickly, effectively and with a suitable degree of
sensitivity, will allow measurement accuracy to be further enhanced and will open the door to numerous applications
within the memory fab environment including process monitoring and improvement. In this paper, we intend to
investigate techniques for detecting asymmetric structures and also for the more complex issue of reconstructing the
shape of these structures.